F-Tile Interlaken Intel® FPGA IP User Guide

ID 683622
Date 1/14/2022
Public

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Document Table of Contents

4.1. Data Path Flow

The Interlaken IP core consists of two paths:
  • Interlaken TX path
  • Interlaken RX path
Each path includes MAC, PCS, and PMA blocks. The PCS blocks are implemented in hard IP. In the NRZ mode, the PCS is interfacing with the PMA directly. In the PAM4 mode, the PCS is interfacing with the Transcode and Alignment block.
Figure 7. NRZ Mode VariationsThe figure illustrates the 8-word data transfer scenario. This figure uses the following conventions:
  • n = Number of calendar pages
  • m = Number of lanes
Figure 8. PAM4 Mode VariationsThe figure illustrates the 16-word data transfer scenario. This figure uses the following conventions:
  • n = Number of calendar pages
  • m = Number of lanes