L- and H-Tile Transceiver PHY User Guide

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ID 683621
Date 1/30/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile 3. PLLs and Clock Networks 4. Resetting Transceiver Channels 5. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture 6. Reconfiguration Interface and Dynamic Reconfiguration 7. Calibration 8. Debugging Transceiver Links A. Logical View of the L-Tile/H-Tile Transceiver Registers
1. Overview x
1.1. L-Tile/H-Tile Layout in Intel® Stratix® 10 Device Variants 1.2. L-Tile/H-Tile Counts in Intel® Stratix® 10 Devices and Package Variants 1.3. L-Tile/H-Tile Building Blocks 1.4. Overview Revision History
1.1. L-Tile/H-Tile Layout in Intel® Stratix® 10 Device Variants x
1.1.1. Intel® Stratix® 10 GX/SX H-Tile Configurations 1.1.2. Intel® Stratix® 10 TX H-Tile and E-Tile Configurations 1.1.3. Intel® Stratix® 10 MX H-Tile and E-Tile Configurations
1.3. L-Tile/H-Tile Building Blocks x
1.3.1. Transceiver Bank Architecture 1.3.2. Transceiver Channel Types 1.3.3. GX and GXT Channel Placement Guidelines 1.3.4. GXT Channel Usage 1.3.5. PLL and Clock Networks 1.3.6. Ethernet Hard IP 1.3.7. PCIe Gen1/Gen2/Gen3 Hard IP Block
1.3.2. Transceiver Channel Types x
1.3.2.1. GX Channel 1.3.2.2. GXT Channel
1.3.5. PLL and Clock Networks x
1.3.5.1. PLLs 1.3.5.2. Input Reference Clock Sources 1.3.5.3. Transceiver Clock Network
1.3.5.1. PLLs x
1.3.5.1.1. Transceiver Phase-Locked Loops 1.3.5.1.2. Clock Generation Block (CGB)
1.3.5.3. Transceiver Clock Network x
1.3.5.3.1. x1 Clock Lines 1.3.5.3.2. x6 Clock Lines 1.3.5.3.3. x24 Clock Lines 1.3.5.3.4. GXT Clock Network
1.3.6. Ethernet Hard IP x
1.3.6.1. 100G Ethernet MAC Hard IP 1.3.6.2. 100G Configuration
2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile x
2.1. Transceiver Design IP Blocks 2.2. Transceiver Design Flow 2.3. Configuring the Native PHY IP Core 2.4. Using the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP Core 2.5. Implementing the PHY Layer for Transceiver Protocols 2.6. Unused or Idle Transceiver Channels 2.7. Simulating the Native PHY IP Core 2.8. Implementing the Transceiver Native PHY Layer in L-Tile/H-Tile Revision History
2.2. Transceiver Design Flow x
2.2.1. Select the PLL IP Core 2.2.2. Reset Controller 2.2.3. Create Reconfiguration Logic 2.2.4. Connect the Native PHY IP Core to the PLL IP Core and Reset Controller 2.2.5. Connect Datapath 2.2.6. Modify Native PHY IP Core SDC 2.2.7. Compile the Design 2.2.8. Verify Design Functionality
2.3. Configuring the Native PHY IP Core x
2.3.1. Protocol Presets 2.3.2. GXT Channels 2.3.3. General and Datapath Parameters 2.3.4. PMA Parameters 2.3.5. PCS-Core Interface Parameters 2.3.6. Analog PMA Settings Parameters 2.3.7. Enhanced PCS Parameters 2.3.8. Standard PCS Parameters 2.3.9. PCS Direct Datapath Parameters 2.3.10. Dynamic Reconfiguration Parameters 2.3.11. Generation Options Parameters 2.3.12. PMA, Calibration, and Reset Ports 2.3.13. PCS-Core Interface Ports 2.3.14. Enhanced PCS Ports 2.3.15. Standard PCS Ports 2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping 2.3.17. IP Core File Locations
2.3.14. Enhanced PCS Ports x
2.3.14.1. Enhanced PCS TX and RX Control Ports
2.3.16. Transceiver PHY PCS-to-Core Interface Reference Port Mapping x
2.3.16.1. PCS-Core Interface Ports: Enhanced PCS 2.3.16.2. PCS-Core Interface Ports: Standard PCS 2.3.16.3. PCS-Core Interface Ports: PCS-Direct
2.4. Using the Intel® Stratix® 10 L-Tile/H-Tile Transceiver Native PHY Intel® Stratix® 10 FPGA IP Core x
2.4.1. PMA Functions 2.4.2. PCS Functions 2.4.3. Deterministic Latency Use Model 2.4.4. Debug Functions
2.4.1. PMA Functions x
2.4.1.1. TX PMA Use Model 2.4.1.2. RX PMA Use Model
2.4.1.2. RX PMA Use Model x
2.4.1.2.1. Using RX in Manual Mode 2.4.1.2.2. Using RX in Adaptive Mode 2.4.1.2.3. Setting RX PMA Adaptation Modes 2.4.1.2.4. Register Sequences
2.4.2. PCS Functions x
2.4.2.1. Receiver Word Alignment 2.4.2.2. Receiver Clock Compensation 2.4.2.3. Encoding/Decoding 2.4.2.4. Running Disparity Control and Check 2.4.2.5. FIFO Operation for the Enhanced PCS 2.4.2.6. Polarity Inversion 2.4.2.7. Data Bitslip 2.4.2.8. Bit Reversal 2.4.2.9. Byte Reversal 2.4.2.10. Double Rate Transfer Mode 2.4.2.11. Asynchronous Data Transfer 2.4.2.12. Low Latency
2.4.2.1. Receiver Word Alignment x
2.4.2.1.1. Word Alignment Using the Standard PCS 2.4.2.1.2. Word Alignment Using the Enhanced PCS
2.4.2.2. Receiver Clock Compensation x
2.4.2.2.1. Clock Compensation Using the Standard PCS 2.4.2.2.2. Clock Compensation Using the Enhanced PCS
2.4.2.3. Encoding/Decoding x
2.4.2.3.1. 8B/10B Encoder and Decoder 2.4.2.3.2. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 2.4.2.3.3. KR-FEC Functionality for 64B/66B Based Protocols
2.4.2.4. Running Disparity Control and Check x
2.4.2.4.1. 8B/10B TX Disparity Control
2.4.2.5. FIFO Operation for the Enhanced PCS x
2.4.2.5.1. Enhanced PCS FIFO Operation
2.4.2.6. Polarity Inversion x
2.4.2.6.1. TX Data Polarity Inversion 2.4.2.6.2. RX Data Polarity Inversion
2.4.2.7. Data Bitslip x
2.4.2.7.1. TX Data Bitslip 2.4.2.7.2. RX Data Bitslip
2.4.2.8. Bit Reversal x
2.4.2.8.1. Transmitter Bit Reversal 2.4.2.8.2. Receiver Bit Reversal
2.4.2.9. Byte Reversal x
2.4.2.9.1. Transmitter Byte Reversal 2.4.2.9.2. Receiver Byte Reversal
2.4.2.10. Double Rate Transfer Mode x
2.4.2.10.1. Word Marking Bits 2.4.2.10.2. How to Implement Double Rate Transfer Mode
2.4.2.11. Asynchronous Data Transfer x
2.4.2.11.1. FPGA Fabric to Transceiver Transfer 2.4.2.11.2. Transceiver to FPGA Fabric Transfer
2.4.2.12. Low Latency x
2.4.2.12.1. How to Enable Low Latency in Basic (Standard PCS) 2.4.2.12.2. How to Enable Low Latency in Basic (Enhanced PCS)
2.4.3. Deterministic Latency Use Model x
2.4.3.1. Phase-measuring FIFOs
2.4.3.1. Phase-measuring FIFOs x
2.4.3.1.1. Primary Use Model 2.4.3.1.2. FIFO Latency Calculation
2.4.4. Debug Functions x
2.4.4.1. Pattern Generators and Verifiers 2.4.4.2. PRBS Soft Accumulators 2.4.4.3. Loopback 2.4.4.4. On-die Instrumentation
2.4.4.1. Pattern Generators and Verifiers x
2.4.4.1.1. Pattern Generator and Verifier Use Model 2.4.4.1.2. Square Wave Pattern Generator 2.4.4.1.3. PRBS Generator and Verifier 2.4.4.1.4. PRBS Control and Status Ports 2.4.4.1.5. Enabling and Disabling the PRBS Generator and PRBS Verifier
2.4.4.2. PRBS Soft Accumulators x
2.4.4.2.1. PRBS Soft Accumulators Use Model
2.4.4.3. Loopback x
2.4.4.3.1. Enabling and Disabling Loopback
2.4.4.4. On-die Instrumentation x
2.4.4.4.1. On-die Instrumentation Overview 2.4.4.4.2. Preserving ODI Performance 2.4.4.4.3. How to Enable ODI 2.4.4.4.4. Scanning the Horizontal Eye Opening 2.4.4.4.5. Scanning the Horizontal and Vertical Phases 2.4.4.4.6. How to Disable ODI 2.4.4.4.7. Horizontal Phase Step Mapping
2.5. Implementing the PHY Layer for Transceiver Protocols x
2.5.1. PCI Express (PIPE) 2.5.2. Interlaken 2.5.3. Ethernet 2.5.4. CPRI
2.5.1. PCI Express (PIPE) x
2.5.1.1. Transceiver Channel Datapath for PIPE 2.5.1.2. Supported PIPE Features 2.5.1.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2.5.1.4. How to Implement PCI Express (PIPE) in Intel® Stratix® 10 Transceivers 2.5.1.5. Native PHY IP Core Parameter Settings for PIPE 2.5.1.6. fPLL IP Core Parameter Settings for PIPE 2.5.1.7. ATX PLL IP Core Parameter Settings for PIPE 2.5.1.8. Native PHY IP Core Ports for PIPE 2.5.1.9. fPLL Ports for PIPE 2.5.1.10. ATX PLL Ports for PIPE 2.5.1.11. Preset Mappings to TX De-emphasis 2.5.1.12. How to Place Channels for PIPE Configurations 2.5.1.13. Link Equalization for Gen3 2.5.1.14. Timing Closure Recommendations
2.5.1.2. Supported PIPE Features x
2.5.1.2.1. Gen1/Gen2 Features 2.5.1.2.2. Gen3 Features
2.5.1.12. How to Place Channels for PIPE Configurations x
2.5.1.12.1. Master Channel in Bonded Configurations
2.5.2. Interlaken x
2.5.2.1. Interlaken Configuration Clocking and Bonding
2.5.2.1. Interlaken Configuration Clocking and Bonding x
2.5.2.1.1. x24 Clock Bonding Scenario 2.5.2.1.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine
2.5.3. Ethernet x
2.5.3.1. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC Variants 2.5.3.2. 40GBASE-R with KR FEC Variant
2.5.3.1. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with KR FEC Variants x
2.5.3.1.1. The XGMII Interface Scheme in 10GBASE-R
2.5.4. CPRI x
2.5.4.1. CPRI Line Rate Revisions 2.5.4.2. Transceiver Channel Datapath and Clocking for CPRI 2.5.4.3. Supported Features for CPRI 2.5.4.4. Deterministic Latency
2.5.4.2. Transceiver Channel Datapath and Clocking for CPRI x
2.5.4.2.1. TX PLL Selection for CPRI 2.5.4.2.2. Auto-Negotiation
2.5.4.3. Supported Features for CPRI x
2.5.4.3.1. Word Aligner in Manual Mode for CPRI
2.7. Simulating the Native PHY IP Core x
2.7.1. How to Specify Third-Party RTL Simulators 2.7.2. Scripting IP Simulation 2.7.3. Custom Simulation Flow
2.7.2. Scripting IP Simulation x
2.7.2.1. Generating a Combined Simulator Setup Script 2.7.2.2. Steps for a .do file for Simulation
2.7.3. Custom Simulation Flow x
2.7.3.1. How to Use the Simulation Library Compiler 2.7.3.2. Custom Simulation Scripts
3. PLLs and Clock Networks x
3.1. PLLs 3.2. Input Reference Clock Sources 3.3. Transmitter Clock Network 3.4. Clock Generation Block 3.5. FPGA Fabric-Transceiver Interface Clocking 3.6. Double Rate Transfer Mode 3.7. Transmitter Data Path Interface Clocking 3.8. Receiver Data Path Interface Clocking 3.9. Channel Bonding 3.10. PLL Cascading Clock Network 3.11. Using PLLs and Clock Networks 3.12. PLLs and Clock Networks Revision History
3.1. PLLs x
3.1.1. ATX PLL 3.1.2. fPLL 3.1.3. CMU PLL
3.1.1. ATX PLL x
3.1.1.1. ATX PLL to fPLL Spacing Requirements 3.1.1.2. Using the ATX PLL for GXT Channels 3.1.1.3. GXT Implementation Usage Restrictions for ATX PLL GX & MCGB 3.1.1.4. Instantiating the ATX PLL IP Core 3.1.1.5. ATX PLL IP Core - Parameters, Settings, and Ports
3.1.2. fPLL x
3.1.2.1. Instantiating the fPLL IP Core 3.1.2.2. fPLL IP Core Constraints 3.1.2.3. fPLL IP Core - Parameters, Settings, and Ports
3.1.3. CMU PLL x
3.1.3.1. Instantiating CMU PLL IP Core 3.1.3.2. CMU PLL IP Core - Parameters, Settings, and Ports
3.2. Input Reference Clock Sources x
3.2.1. Dedicated Reference Clock Pins 3.2.2. Receiver Input Pins 3.2.3. PLL Cascading as an Input Reference Clock Source 3.2.4. Reference Clock Network 3.2.5. Core Clock as an Input Reference Clock
3.2.1. Dedicated Reference Clock Pins x
3.2.1.1. Reference Clock I/O Standard 3.2.1.2. Dedicated Reference Clock Pin Termination (XCVR_S10_REFCLK_TERM_TRISTATE)
3.3. Transmitter Clock Network x
3.3.1. x1 Clock Lines 3.3.2. x6 Clock Lines 3.3.3. x24 Clock Lines 3.3.4. GXT Clock Network 3.3.5. HCLK Network
3.9. Channel Bonding x
3.9.1. PMA Bonding 3.9.2. PMA and PCS Bonding 3.9.3. Selecting Channel Bonding Schemes 3.9.4. Skew Calculations
3.9.1. PMA Bonding x
3.9.1.1. x6/x24 Bonding
3.11. Using PLLs and Clock Networks x
3.11.1. Non-bonded Configurations 3.11.2. Bonded Configurations 3.11.3. Implementing PLL Cascading 3.11.4. Mix and Match Example
3.11.1. Non-bonded Configurations x
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration 3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration 3.11.1.3. Implementing Multi-Channel x24 Non-Bonded Configuration
3.11.2. Bonded Configurations x
3.11.2.1. Implementing x6/x24 Bonding Mode
4. Resetting Transceiver Channels x
4.1. When Is Reset Required? 4.2. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Implementation 4.3. How Do I Reset? 4.4. Using PCS Reset Status Port 4.5. Using Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP 4.6. Using a User-Coded Reset Controller 4.7. Combining Status or PLL Lock Signals with User Coded Reset Controller 4.8. Resetting Transceiver Channels Revision History
4.3. How Do I Reset? x
4.3.1. Recommended Reset Sequence 4.3.2. Transceiver Blocks Affected by Reset and Power-down Signals
4.3.1. Recommended Reset Sequence x
4.3.1.1. Resetting the Transmitter After Power Up 4.3.1.2. Resetting the Transmitter During Device Operation 4.3.1.3. Resetting the Receiver After Power Up 4.3.1.4. Resetting the Receiver During Device Operation (Auto Mode) 4.3.1.5. Clock Data Recovery in Manual Lock Mode 4.3.1.6. Special TX PCS Reset Release Sequence
4.3.1.5. Clock Data Recovery in Manual Lock Mode x
4.3.1.5.1. Control Settings for CDR Manual Lock Mode 4.3.1.5.2. Resetting the Transceiver in CDR Manual Lock Mode
4.3.1.6. Special TX PCS Reset Release Sequence x
4.3.1.6.1. TX Core FIFO in Interlaken/Basic Mode 4.3.1.6.2. Double Rate Transfer Mode enabled 4.3.1.6.3. TX Gearbox Ratio *:67
4.5. Using Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP x
4.5.1. Parameterizing Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP 4.5.2. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Parameters 4.5.3. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Interfaces 4.5.4. Transceiver PHY Reset Controller Intel® Stratix® 10 FPGA IP Resource Utilization
4.6. Using a User-Coded Reset Controller x
4.6.1. User-Coded Reset Controller Signals
5. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture x
5.1. PMA Architecture 5.2. Enhanced PCS Architecture 5.3. Intel® Stratix® 10 Standard PCS Architecture 5.4. Intel® Stratix® 10 PCI Express Gen3 PCS Architecture 5.5. PCS Support for GXT Channels 5.6. Square Wave Generator 5.7. PRBS Pattern Generator 5.8. PRBS Pattern Verifier 5.9. Loopback Modes 5.10. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture Revision History
5.1. PMA Architecture x
5.1.1. Transmitter PMA 5.1.2. Receiver PMA
5.1.1. Transmitter PMA x
5.1.1.1. Serializer 5.1.1.2. Transmitter Buffer
5.1.1.2. Transmitter Buffer x
5.1.1.2.1. High-Speed Differential I/O 5.1.1.2.2. Programmable Output Differential Voltage 5.1.1.2.3. Programmable Pre-Emphasis
5.1.2. Receiver PMA x
5.1.2.1. Receiver Buffer 5.1.2.2. Clock Data Recovery (CDR) Unit 5.1.2.3. Deserializer
5.1.2.1. Receiver Buffer x
5.1.2.1.1. Programmable Differential On-Chip Termination (OCT) 5.1.2.1.2. Signal Detector 5.1.2.1.3. Continuous Time Linear Equalization (CTLE) 5.1.2.1.4. Variable Gain Amplifier (VGA) 5.1.2.1.5. Adaptive Parametric Tuning (ADAPT) Engine 5.1.2.1.6. Decision Feedback Equalization (DFE) 5.1.2.1.7. On-Die Instrumentation
5.1.2.2. Clock Data Recovery (CDR) Unit x
5.1.2.2.1. Lock-to-Reference Mode 5.1.2.2.2. Lock-to-Data Mode 5.1.2.2.3. CDR Lock Modes
5.2. Enhanced PCS Architecture x
5.2.1. Transmitter Datapath 5.2.2. Receiver Datapath 5.2.3. RX KR FEC Blocks
5.2.1. Transmitter Datapath x
5.2.1.1. TX Core FIFO 5.2.1.2. TX PCS FIFO 5.2.1.3. Interlaken Frame Generator 5.2.1.4. Interlaken CRC-32 Generator 5.2.1.5. 64B/66B Encoder and Transmitter State Machine (TX SM) 5.2.1.6. Scrambler 5.2.1.7. Interlaken Disparity Generator 5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion 5.2.1.9. KR FEC Blocks
5.2.2. Receiver Datapath x
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion 5.2.2.2. Block Synchronizer 5.2.2.3. Interlaken Disparity Checker 5.2.2.4. Descrambler 5.2.2.5. Interlaken Frame Synchronizer 5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) 5.2.2.7. 10GBASE-R Bit-Error Rate (BER) Checker 5.2.2.8. Interlaken CRC-32 Checker 5.2.2.9. RX PCS FIFO 5.2.2.10. RX Core FIFO
5.2.2.9. RX PCS FIFO x
5.2.2.9.1. Phase Compensation Mode 5.2.2.9.2. Register Mode
5.2.2.10. RX Core FIFO x
5.2.2.10.1. Phase Compensation Mode 5.2.2.10.2. Register Mode 5.2.2.10.3. Basic Mode 5.2.2.10.4. Interlaken Mode 5.2.2.10.5. 10GBASE-R Mode
5.3. Intel® Stratix® 10 Standard PCS Architecture x
5.3.1. Transmitter Datapath 5.3.2. Receiver Datapath
5.3.1. Transmitter Datapath x
5.3.1.1. TX Core FIFO 5.3.1.2. TX PCS FIFO 5.3.1.3. Byte Serializer 5.3.1.4. 8B/10B Encoder 5.3.1.5. Polarity Inversion Feature 5.3.1.6. TX Bit Slip
5.3.1.3. Byte Serializer x
5.3.1.3.1. Bonded Byte Serializer 5.3.1.3.2. Byte Serializer Disabled Mode 5.3.1.3.3. Byte Serializer Serialize x2 Mode 5.3.1.3.4. Byte Serializer Serialize x4 Mode
5.3.1.4. 8B/10B Encoder x
5.3.1.4.1. 8B/10B Encoder Control Code Encoding 5.3.1.4.2. 8B/10B Encoder Reset Condition 5.3.1.4.3. 8B/10B Encoder Idle Character Replacement Feature 5.3.1.4.4. 8B/10B Encoder Current Running Disparity Control Feature 5.3.1.4.5. 8B/10B Encoder Bit Reversal Feature 5.3.1.4.6. 8B/10B Encoder Byte Reversal Feature
5.3.2. Receiver Datapath x
5.3.2.1. Word Aligner 5.3.2.2. RX Polarity Inversion Feature 5.3.2.3. Rate Match FIFO 5.3.2.4. 8B/10B Decoder 5.3.2.5. PRBS Verifier 5.3.2.6. Byte Deserializer 5.3.2.7. RX PCS FIFO 5.3.2.8. RX Core FIFO
5.3.2.1. Word Aligner x
5.3.2.1.1. Word Aligner Bitslip Mode 5.3.2.1.2. Word Aligner Manual Mode 5.3.2.1.3. Word Aligner Synchronous State Machine Mode 5.3.2.1.4. Word Aligner Deterministic Latency Mode 5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes 5.3.2.1.6. Word Aligner RX Bit Reversal Feature 5.3.2.1.7. Word Aligner RX Byte Reversal Feature
5.3.2.4. 8B/10B Decoder x
5.3.2.4.1. 8B/10B Decoder Control Code Encoding 5.3.2.4.2. 8B/10B Decoder Running Disparity Checker Feature
5.3.2.6. Byte Deserializer x
5.3.2.6.1. Byte Deserializer Disabled Mode 5.3.2.6.2. Byte Deserializer Deserialize x2 Mode 5.3.2.6.3. Byte Deserializer Deserialize x4 Mode 5.3.2.6.4. Bonded Byte Deserializer 5.3.2.6.5. Byte Ordering Register-Transfer Level (RTL) 5.3.2.6.6. Byte Serializer Effects on Data Propagation at the RX Side 5.3.2.6.7. ModelSim Byte Ordering Analysis
5.4. Intel® Stratix® 10 PCI Express Gen3 PCS Architecture x
5.4.1. Transmitter Datapath 5.4.2. Receiver Datapath 5.4.3. PIPE Interface
5.4.1. Transmitter Datapath x
5.4.1.1. TX Core FIFO 5.4.1.2. TX PCS FIFO 5.4.1.3. Gearbox
5.4.2. Receiver Datapath x
5.4.2.1. Block Synchronizer 5.4.2.2. Rate Match FIFO 5.4.2.3. RX PCS FIFO 5.4.2.4. RX Core FIFO
5.4.3. PIPE Interface x
5.4.3.1. Auto-Speed Negotiation 5.4.3.2. Clock Data Recovery Control
6. Reconfiguration Interface and Dynamic Reconfiguration x
6.1. Reconfiguring Channel and PLL Blocks 6.2. Interacting with the Reconfiguration Interface 6.3. Multiple Reconfiguration Profiles 6.4. Arbitration 6.5. Recommendations for Dynamic Reconfiguration 6.6. Steps to Perform Dynamic Reconfiguration 6.7. Direct Reconfiguration Flow 6.8. Native PHY IP or PLL IP Core Guided Reconfiguration Flow 6.9. Reconfiguration Flow for Special Cases 6.10. Changing Analog PMA Settings 6.11. Ports and Parameters 6.12. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks 6.13. Embedded Debug Features 6.14. Timing Closure Recommendations 6.15. Unsupported Features 6.16. Transceiver Register Map 6.17. Reconfiguration Interface and Dynamic Revision History
6.2. Interacting with the Reconfiguration Interface x
6.2.1. Reading from the Reconfiguration Interface 6.2.2. Writing to the Reconfiguration Interface
6.3. Multiple Reconfiguration Profiles x
6.3.1. Configuration Files 6.3.2. Embedded Reconfiguration Streamer
6.6. Steps to Perform Dynamic Reconfiguration x
6.6.1. Channel Reconfiguration 6.6.2. PLL Reconfiguration
6.9. Reconfiguration Flow for Special Cases x
6.9.1. Switching Transmitter PLL 6.9.2. Switching Reference Clocks 6.9.3. Reconfiguring Between GX and GXT Channels
6.9.2. Switching Reference Clocks x
6.9.2.1. ATX Reference Clock Switching 6.9.2.2. fPLL Reference Clock Switching 6.9.2.3. CDR and CMU Reference Clock Switching
6.13. Embedded Debug Features x
6.13.1. Native PHY Debug Master Endpoint (NPDME) 6.13.2. Optional Reconfiguration Logic
6.13.2. Optional Reconfiguration Logic x
6.13.2.1. Capability Registers 6.13.2.2. Control and Status Registers 6.13.2.3. PRBS Soft Accumulators
7. Calibration x
7.1. Reconfiguration Interface and Arbitration with PreSICE (Precision Signal Integrity Calibration Engine) 7.2. Calibration Registers 7.3. Power-up Calibration 7.4. Background Calibration 7.5. User Recalibration 7.6. Calibration Revision History
7.2. Calibration Registers x
7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers 7.2.2. User Recalibration Enable Registers 7.2.3. Capability Registers 7.2.4. Rate Switch Flag Register
7.2.2. User Recalibration Enable Registers x
7.2.2.1. Transceiver Channel Calibration Registers 7.2.2.2. ATX PLL/fPLL/CMU PLL Calibration Registers
7.5. User Recalibration x
7.5.1. Recalibrating a Duplex Channel (Both PMA TX and PMA RX) 7.5.2. Recalibrating the PMA RX Only in a Duplex Channel 7.5.3. Recalibrating the PMA TX Only in a Duplex Channel 7.5.4. Recalibrating a PMA Simplex RX Without a Simplex TX Merged into the Same Physical Channel 7.5.5. Recalibrating a PMA Simplex TX Without a Simplex RX Merged into the Same Physical Channel 7.5.6. Recalibrating Only a PMA Simplex RX in a Simplex TX Merged Physical Channel 7.5.7. Recalibrating Only a PMA Simplex TX in a Simplex RX Merged Physical Channel 7.5.8. Recalibrating the fPLL 7.5.9. Recalibrating the ATX PLL 7.5.10. Recalibrating the CMU PLL When it is Used as a TX PLL
8. Debugging Transceiver Links x
8.1. Transceiver Toolkit GUI 8.2. Transceiver Debugging Flow Walkthrough 8.3. Linking Hardware Resource for Multiple FPGAs 8.4. Troubleshooting Common Errors 8.5. Debugging Transceiver Links Revision History
8.1. Transceiver Toolkit GUI x
8.1.1. Collection View
8.2. Transceiver Debugging Flow Walkthrough x
8.2.1. Enabling Transceiver Toolkit Support 8.2.2. Programming the Design into an Intel FPGA 8.2.3. Loading the Design to the Transceiver Toolkit 8.2.4. Creating Transceiver Links 8.2.5. Verifying Hardware Connections 8.2.6. Running Link Tests
8.2.4. Creating Transceiver Links x
8.2.4.1. Transceiver Toolkit Parameter Settings
8.2.6. Running Link Tests x
8.2.6.1. Running BER Tests 8.2.6.2. Link Optimization Tests 8.2.6.3. Running Eye Viewer Tests
8.3. Linking Hardware Resource for Multiple FPGAs x
8.3.1. Linking One Design to One Device 8.3.2. Linking Two Designs to Two Devices 8.3.3. Linking One Design on Two Devices 8.3.4. Linking Designs and Devices on Separate Boards
A. Logical View of the L-Tile/H-Tile Transceiver Registers x
A.1. ATX_PLL Logical Register Map A.2. CMU_PLL Logical Register Map A.3. FPLL Logical Register Map A.4. Channel Logical Register Map A.5. Transmitter PLL Switching Register Map A.6. Logical View Register Map of the L-Tile/H-Tile Transceiver Registers Revision History
A.1. ATX_PLL Logical Register Map x
A.1.1. ATX PLL Calibration A.1.2. Optional Reconfiguration Logic ATX PLL- Capability A.1.3. Optional Reconfiguration Logic ATX PLL- Control & Status A.1.4. Embedded Streamer (ATX PLL) A.1.5. Updating ATX PLL Fractional Multiply Factor (K) Value
A.2. CMU_PLL Logical Register Map x
A.2.1. CDR/CMU and PMA Calibration A.2.2. Optional Reconfiguration Logic CMU PLL- Capability A.2.3. Optional Reconfiguration Logic CMU PLL- Control & Status A.2.4. Embedded Streamer (CMU PLL)
A.3. FPLL Logical Register Map x
A.3.1. fPLL Calibration A.3.2. Optional Reconfiguration Logic fPLL-Capability A.3.3. Optional Reconfiguration Logic fPLL-Control & Status A.3.4. Embedded Streamer (fPLL) A.3.5. Updating fPLL Fractional Multiply Factor (K) Value
A.4. Channel Logical Register Map x
A.4.1. Transmitter PMA Logical Register Map A.4.2. Receiver PMA Logical Register Map A.4.3. Pattern Generators and Checkers A.4.4. Loopback A.4.5. Optional Reconfiguration Logic PHY- Capability A.4.6. Optional Reconfiguration Logic PHY- Control & Status A.4.7. Embedded Streamer (Native PHY) A.4.8. Static Polarity Inversion A.4.9. Reset A.4.10. CDR/CMU and PMA Calibration
A.4.1. Transmitter PMA Logical Register Map x
A.4.1.1. Pre-emphasis A.4.1.2. VOD A.4.1.3. TX Compensation A.4.1.4. Slew Rate A.4.1.5. TX Termination
A.4.2. Receiver PMA Logical Register Map x
A.4.2.1. RX Bandwidth Selection A.4.2.2. RX Termination A.4.2.3. Setting RX PMA Adaptation Modes A.4.2.4. Manual CTLE A.4.2.5. Manual VGA A.4.2.6. Adaptation Control - Start A.4.2.7. Adaptation Control - Stop A.4.2.8. Adapted Value Readout
A.4.3. Pattern Generators and Checkers x
A.4.3.1. Square Wave Generator A.4.3.2. PRBS Generator A.4.3.3. PRBS Verifier A.4.3.4. Other registers needed for PRBS Verifier A.4.3.5. PRBS Soft Accumulators
1. Overview
2. Implementing the Transceiver PHY Layer in L-Tile/H-Tile
3. PLLs and Clock Networks
4. Resetting Transceiver Channels
5. Intel® Stratix® 10 L-Tile/H-Tile Transceiver PHY Architecture
6. Reconfiguration Interface and Dynamic Reconfiguration
7. Calibration
8. Debugging Transceiver Links
A. Logical View of the L-Tile/H-Tile Transceiver Registers

2.8. Implementing the Transceiver Native PHY Layer in L-Tile/H-Tile Revision History

Document Version Changes
2024.01.30 Made the following changes:
  • Changed rx_set_lockedtoref to rx_set_locktoref in RX PMA Optional Ports table.
  • Changed rx_set_lockedtodata to rx_set_locktodata in RX PMA Optional Ports table.
2023.10.05 Added note about how to tie tx_err_ins port for non-Interlaken modes in the Enhanced PCS Parameters, Enhanced PCS Ports, and Enhanced PCS TX and RX Control Ports sections.
2023.02.20 Added note about the simulation model compilation in the How to Use the Simulation Library Compiler section.
2023.02.01 Added note for rx_pma_clkslip in RX PMA Ports table in PMA, Calibration, and Reset Ports section.
2022.03.28
  • Added note to TX Analog PMA Settings Options table that the Intel® Stratix® 10 L-Tile/H-Tile Pre-emphasis and Output Swing Estimator tool is only supported for ES devices.
  • Updated PCS-Core Interface Parameters table with Enable TX Data Valid Gen manual setting parameter.
  • Updated Preserving ODI performance section with Intel® Quartus® Prime software qsf settings to preserve ODI performance.
  • Modified Using RX in Adaptive Mode section to check rx_analogreset_stat is asserted before starting adaptation.
2021.12.13
  • Updated Analog PMA Settings Parameters section with Start PMA DFE adaptation auto feature.
  • Updated RX Analog PMA Settings Options table with Start PMA DFE adaptation auto parameter.
  • Updated Enable rx_std_signaldetect port parameter description to support only PCI Express, SATA and SAS protocol modes in Bit Reversal and Polarity Inversion table.
  • Updated rx_std_signaldetect[<n>-1:0] port description to support only PCI Express, SATA and SAS protocol modes in RX PMA Ports table.
2021.10.04
  • Updated the value for the RX On-chip Termination parameter in the RX Analog PMA Settings Options table.
  • Added note to the PCIe Ports table in the Standard PCS Parameters section.
2021.09.09
  • Added new topic: Preserving ODI Performance
  • Updated the step and added a note in the How to Disable ODI section.
  • Added footnote for ×16 PIPE configuration in the Logical PCS Master Channel for PIPE Configuration when the AUTO Selection is Enabled table.
  • Added the following diagrams for Intel® Stratix® 10 GX 10M devices:
    • x2 Configuration (for Intel® Stratix® 10 GX 10M Devices)
    • x4 Configuration (for Intel® Stratix® 10 GX 10M Devices)
    • x8 Configuration (for Intel® Stratix® 10 GX 10M Devices)
  • Updated the steps to preserve the performance of the channel during idle state in the Unused or Idle Transceiver Channels section.
  • Removed references to the NCSim simulator.
2021.06.10
  • Updated the Gen3 PIPE value for the Number of TX PLL clock inputs per channel parameter in the TX PMA Options table.
  • Updated the Gen3 PIPE value for the PCI Express Gen3 rate match FIFO mode parameter in the Standard PCS Options table.
  • Updated the Gen3 PIPE values for the TX FIFO partially full threshold and RX FIFO partially full threshold parameters in the PCS-Core Interface Options table.
2021.03.29
  • Updated the PCS-Core Interface Parameters table.
    • Added osc_transfer_en port for the Enable PCS reset status ports parameter.
    • Added descriptions for the output ports for the Enable PCS reset status ports parameter.
  • Updated description for Selected tx_clkout clock source parameter in the TX Clock Options table.
  • Added a note and updated the value for the RX On-chip Termination parameter in the RX Analog PMA Settings Options table.
  • Updated the steps when the RX adaptation mode is set to manual in the How to Enable ODI and How to Disable ODI sections.
  • Corrected the Parallel Clock frequency in the Transceiver Channel Datapath and Clocking for 10GBASE-R (PCS-PMA Interface Width = 32 Bits) diagram.
  • Updated the MCGB input clock frequency parameter value for Gen3 PIPE mode in the ATX PLL Parameters for PCIe PIPE Gen1, Gen2, and Gen3 Modes table.

2020.12.02

 Made the following changes to Analog PMA Settings Parameters:
  • Added instructions on how to verify that the .qsf assignments are recognized by the Intel® Quartus® Prime Pro Edition Assignment Editor.
  • For Output Swing Level (VOD), changed TX_VOD_NO_JITCOMP_DC_L0 to powerdown_tx_vod_no_jitcomp.
  • For Output Swing Level (VOD), add a note:
    Note: For powerdown_tx_vod_no_jitcomp, if the reference clock is paused or not available during operation, both TX buffer positive and negative pins are equal to the TX output common mode voltage (VOCM). For the VOCM value, refer to the Intel® Stratix® 10 Device Data Sheet.
  • For High Speed Compensation, clarified that disable is only for PCIe* Gen1 and Gen2 mode. Refer to the "Parameters for the Native PHY IP Core in PIPE Gen1, Gen2, Gen3 Modes - Analog PMA Settings" table for details.
2020.10.22 Made the following change:
  • Identified the rx_std_wa_patternalign port in two figures as an input (it was previously identified incorrectly as an output).
2020.10.05 Made the following changes:
  • Clarified that the square wave generator is available in 64-bit PCS-PMA data widths only.
  • Clarified that, when using even gear ratios in RX Core FIFO basic mode, you must use the rx_data_valid signal.
2020.03.03 Made the following changes:
  • Updated the following figures to make it clear that rx_clkout is driven by CDR.
    • FIFO Latency Calculation
    • Transceiver Channel Datapath for PIPE Gen1/Gen2 Configurations
    • Transceiver Channel Datapath for PIPE Gen1/Gen2/Gen3 Configurations
    • PCIe* Reverse Parallel Loopback Mode Datapath
    • Transceiver Channel Datapath and Clocking for Interlaken
    • Transceiver Channel Datapath and Clocking for 10GBASE-R (PCS-PMA Interface Width = 32 Bits)
    • Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2 (PCS-PMA Interface Width = 32 Bits)
    • Transceiver Channel Datapath and Clocking for 10GBASE-R with KR FEC (PCSPMA interface width = 64 bits)
    • Transceiver Channel Datapath and Clocking for 40GBASE-R with KR FEC (PCSPMA interface width = 64 bits)
    • Transceiver Channel Datapath and Clocking for CPRI using the Standard PCS
    • Transceiver Channel Datapath and Clocking for CPRI using the Enhanced PCS
  • Clarified ODI support for L-Tile.
  • Updated Unused or Idle Transceiver Channels.
2020.01.29 Made the following change:
  • Added "Implements in core logic" to the "Encoding Scheme" column in CPRI Line Rate Revisions and changed the PCS column from “Enhanced PCS” to “PCS Direct.”
2019.10.02 Made the following changes:
  • For TX Core Interface FIFO Mode > Register and RX PCS-Core Interface FIFO Mode > Register, added the restriction that "This mode is limited to PCS Direct with interface widths of 40 bits or less."
  • Added the Enable PIPE EIOS RX protection parameter in the "General, Common PMA Options, and Datapath Options" table.
2019.06.07 Made the following changes:
  • Added two parameters to the Pre-Emphasis First Pre-Tap Polarity setting in Analog PMA Settings Parameters.
  • Added clarification about the polarity inversion support differences between Standard and Enhanced PCS to Polarity Inversion.
2019.03.22 Made the following changes:
  • Added assignments for "Output Swing Level (VOD)" and "Pre-Emphasis First Post-Tap Polarity."
  • Updated How to Enable ODI, Scanning the Horizontal Eye Opening, Scanning the Horizontal and Vertical Phases, and How to Disable ODI.
2018.10.23 Made the following change:
  • Changed rx_enh_data_valid in the "RX PCS-Core Interface FIFO" table to an output.
2018.10.05 Made the following changes:
  • Changed the pin requirements for OSC_CLK_1 in the "Unused or Idle Transceiver Channels" section.
  • Changed the FIFO mode from Register to Phase Compensation in the "Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2 (PCS-PMA Interface Width = 32 Bits)" figure.
  • Changed the critical warning messages in the "Unused or Idle Transceiver Channels" section.
  • Added note to the "Simulating the Native PHY IP Core" section.
  • Changed the direction of the rx_word_marking_bit port in the "RX PCS-Core Interface Ports: Parallel Data, Control, and Clocks" table.
  • Changed the preset coefficients recommendation in the "Preset Mappings to TX De-emphasis" section.
  • Changed the preset coefficients recommendation in the "Link Equalization for Gen3" section.
  • Changed the 10GBASE-R configuration description in the "Enhanced PCS FIFO Operation" section.
2018.07.06 Made the following changes:
  • Clarified the values for the Slew Rate Control parameter in the "TX Analog PMA Settings Options" table.
  • Clarified the attribute values for slew rate in the "Transmitter QSF Assignment Attributes" table.
  • Removed the note about the rx_std_wa_patternalign port from the "Word Aligner Synchronous State Machine Mode" section.
  • Changed the "Transceiver Channel Datapath and Clocking for 10GBASE-R with IEEE 1588v2 (PCS-PMA Interface Width = 32 Bits)" figure.
  • Clarified the requirements for rx_fifo_align_clr duration in the "RX Multi-lane FIFO Deskew State Machine" section.
  • Clarified the requirement for rx_fifo_align_clr duration on exit from reset in the "State Flow of the RX FIFO Deskew" figure.
  • Changed the description of rx_std_byterev_ena[<n>-1:0] in the "Bit Reversal and Polarity Inversion" table.
  • Added a note about designing with the Use default TX PMA analog settings and Use default RX PMA analog settings options as a starting point in the "Analog PMA Settings Parameters" section.
  • Added further description of the Provide sample QSF assignments in the "Sample QSF Assignment Option" table.
  • Changed the PCS-PMA width to 32 in the "Transceiver Channel Datapath and Clocking for 10GBASE-R (PCS-PMA Interface Width = 32 Bits)" figure.
  • Changed the command to disable the warning message for unused transceiver channels in the "Unused or Idle Transceiver Channels" section.
  • Added QSF syntax examples for most of the parameters in the "TX Analog PMA Settings Options" table.
  • Added QSF syntax examples for most of the parameters in the "RX Analog PMA Settings Options" table.
  • Changed the data rate ranges and register settings in the "ODI Bandwidth Settings" table.
  • Changed Scanning the Horizontal Eye Opening.
  • Changed Scanning the Horizontal and Vertical Phases.
  • Added a footnote to the code_violation_status signal in the "Simplified Data Interface=Disabled, Double-Rate Transfer=Enabled" table.
  • Updated the critical warning message in the "Unused or Idle Transceiver Channels" section.
  • Added clarification about the adaptation engine in the "Using RX in Adaptive Mode" section.
  • Added ODI support on L-Tile devices in the "On-die Instrumentation" section.
  • Changed the base data rate for the 12165.12 Mbps data rate in the "Recommended Base Data Rates and Clock Generation Blocks for Available Data Rates" table.
  • Added an example to the per-pin .qsf assignment instruction in the "Unused or Idle Transceiver Channels" section.
2018.03.16 Made the following changes:
  • Changed the functionality and description ofrx_control bit [9:8] to "Unused" in the "Bit Encodings for Basic (Enhanced PCS) with 66-bit word, Basic with KR FEC, 40GBASE-R with KR FEC" table.
  • Added steps 5, 6, and 12 in the "How to Implement Double Rate Transfer Mode" section.
  • Changed the following figures in the "RX Bitslip" section:
    • "RX Bitslip in 8-bit Mode"
    • "RX Bitslip in 10-bit Mode"
    • "RX Bitslip in 16-bit Mode"
    • "RX Bitslip in 20-bit Mode"
  • Changed the following figure in the "Word Aligner Manual Mode" section:
    • "Manual Mode when the PCS-PMA Interface Width is 8 Bits"
  • Added details about how to enable the transceiver toolkit capability in the "Dynamic Reconfiguration Parameters" section.
  • Added the Enable tx_coreclkin2 port parameter to the "PCS-Core Interface Parameters" table.
  • Added the RX PMA analog mode rules parameter to the "Analog PMA Settings" table.
  • Removed the "Manual Mode when the PCS-PMA Interface Width is 10 Bits" figure.
  • Removed the "Manual Mode when the PCS-PMA Interface Width is 16 Bits" figure.
  • Removed the "Manual Mode when the PCS-PMA Interface Width is 20 Bits" figure.
  • Changed the "Synchronization State Machine Mode when the PCS-PMA Interface Width is 20 Bits" figure.
  • Removed the "Word Aligner in Deterministic Latency Mode Waveform" figure.
  • Removed the "High BER" figure.
  • Removed the "Block Lock Assertion" figure.
  • Changed the "Idle Ordered-Set Generation Example" figure.
  • Changed the "RX Polarity Inversion" figure.
  • Changed the following figures in the "RX Data Bitslip" section:
    • "RX Bitslip in 8-bit Mode"
    • "RX Bitslip in 10-bit Mode"
    • "RX Bitslip in 16-bit Mode"
    • "RX Bitslip in 20-bit Mode"
  • Changed the "TX Bit Reversal" figure.
  • Changed the "RX Bit Reversal" figure.
  • Changed the "TX Byte Reversal" figure.
  • Changed the "RX Byte Reversal" figure.
  • Updated the value of the Output Swing Level (VOD) parameter in the "TX Analog PMA Settings Options" table.
  • Changed the descriptions for the following parameters in the "RX Analog PMA Settings Options" table:
    • CTLE AC Gain
    • CTLE EQ Gain
    • VGA DC Gain
  • Added clarification about ways to configure TX PMA settings in the "TX PMA Use Model" section.
  • Added clarification about ways to select your CTLE gain value in the "Manual Mode" section.
  • Defined the SKP symbol and added a note describing why it is used in the "Gen1 and Gen2 Clock Compensation" section.
  • Changed the values or added descriptions for the following parameters in the "TX Analog PMA Settings Options" table:
    • Output Swing Level (VOD)
    • Pre-Emphasis First Pre-Tap Polarity
    • Pre-Emphasis First Pre-Tap Magnitude
    • Pre-Emphasis First Post -Tap Polarity
    • Pre-Emphasis First Post -Tap Magnitude
    • On-Chip Termination
    • Slew Rate Control
  • Changed the values or added descriptions for the following parameters in the "RX Analog PMA Settings Options" table:
    • RX On-chip Termination
    • CTLE AC Gain
    • CTLE EQ Gain
    • VGA DC Gain
  • Changed the "Synchronization State Machine Mode when the PCS-PMA Interface Width is 16 Bits" figure.
  • Changed the "Word Aligner in Deterministic Latency Mode 16 Bits Waveform" figure.
  • Changed the following figures in the TX Data Bit Slip section:
    • TX Bitslip in 8-bit Mode
    • TX Bitslip in 10-bit Mode
    • TX Bitslip in 16-bit Mode
    • TX Bitslip in 20-bit Mode
  • Changed the "Idle Oredered-Set Generation Example" figure.
  • Changed the polarity inversion mode selections in the "RX Data Polarity Inversion" section.
  • Changed the bit reversal mode selections in the "Transmitter Bit Reversal" section.
  • Changed the bit reversal mode selections in the "Receiver Bit Reversal" section.
  • Changed the byte reversal mode selections in the "Receiver Byte Reversal" section.
  • Changed the byte reversal mode selections in the "Transmitter Byte Reversal" section.
  • Changed the note in the "Debug Functions" section.
  • Changed the note in the "On-die Instrumentation" section.
  • Added further description to the rx_set_locktoref[<n>-1:0] and rx_set_locktoref[<n>-1:0] ports in the "RX PMA Ports" table.
  • Added a note to the "Transceiver PHY PCS-to-Core Interface Reference Port Mapping" section.
  • Added description for how to enable/disable serial loopback in the "Enabling and Disabling Loopback" section.
  • Changed the list of restrictions for placing channels for PIPE configurations in the "How to Place Channels for PIPE Configurations" section.
  • Changed the name of the Rate Match modes in the "Clock Compensation Using the Standard PCS" section.
  • Added a sentence for "Enable TX bit/byte reversal" parameter: "TX bit/byte reversal ports are not available but can be changed via soft registers. RX bit reversal ports are available."
  • Added "rx_syncstatus is bus dependent on the width of the parallel data. For example, when the parallel data width is 32 bits, then rx_syncstatus is a 4 bit bus. The final expected value is 1'hf, indicating the control character is identified at the correct location in the 32 bit parallel word." to the "rx_syncstatus[<n><w>/<s>-1:0]".
  • Added "The 2 alignment markers valid status is captured in the 2 bit of rx_std_wa_ala2size signal. When both the markers are matched, then the value of the signal is 2'b11." to "rx_std_wa_a1a2size[<n>-1:0]".
  • Added the "Timing Closure Recommendations" section.
  • Added the two available PIPE refclk assignment settings to "Native PHY IP Core Parameter Settings for PIPE."
2017.08.11 Made the following changes:
  • Added link to the PCIe solutions guidelines in the "Configuring the Native PHY IP Core" section.
  • Added details about the number of GXT channels supported per tile in the "GXT Channels" section.
  • Changed the description for the Enable rx_pma_clkslip port parameter in the "RX PMA Optional Ports" table.
  • Added units of measure to the RX On-chip Termination parameter values in the "RX Analog PMA Settings Options" table.
  • Added descriptions for the following parameters in the "KR-FEC Parameters" table:
    • Enable tx_enh_frame port
    • Enable rx_enh_frame port
    • Enable rx_enh_frame_diag_status port
  • Added further description to the PCI Express Gen3 rate match FIFO mode parameter in the "Rate Match FIFO Parameters" table.
  • Changed the description of the Share reconfiguration interface parameter in the "Dynamic Reconfiguration" table.
  • Changed the direction and updated the description of the rx_pma_clkslip signal in the "RX PMA Ports" table.
  • Changed the clock domains of the following signals in the "TX PCS-Core Interface FIFO" table:
    • tx_fifo_empty[<n>-1:0]
    • tx_fifo_pempty[<n>-1:0]
    • rx_fifo_full[<n>-1:0]
    • rx_fifo_pfull[<n>-1:0]
  • Added the "Calculating Latency through the Word Aligner" section.
  • Added the "CPRI Line Rate Revisions" table.
  • Changed the "Transceiver Channel Datapath and Clocking for CPRI using the Standard PCS" figure.
  • Added the "Clock Frequencies for Various CPRI Data Rates using the Standard PCS" table.
  • Added the "Transceiver Channel Datapath and Clocking for CPRI using the Enhanced PCS" figure.
  • Added the "Clock Frequencies for Various CPRI Data Rates using the Enhanced PCS" table.
  • Added the "FIFO Latency Calculation" section.
  • Added the CPRI chapter.
  • Updated the descriptions for the Enable rx_fifo_pfull port and Enable rx_fifo_pempty port parameters in the " PCS-Core Interface Parameters" table.
  • Added descriptions for the CTLE AC Gain, CTLE EQ Gain, and VGA DC Gain parameters in the "RX Analog PMA Settings Options" table.
  • Updated the descriptions for the tx_fifo_pfull[<n>-1:0] and tx_fifo_pempty[<n>-1:0] ports in the "TX PCS-Core Interface FIFO" table.
  • Added the PCIe Adaptive Mode column to and changed the bit settings for adp_dc_ctle_mode_sel, adp_dc_ctle_mode0_win_start, adp_dc_ctle_onetime, and adp_vga_ctle_low_limit in the "RX Adaption Mode Attributes" table.
  • Changed the footnote in the "Register Chain Minimum Hold Time Calculations" table.
  • Completely restructured the table in and added supporting text to the "Transceiver to FPGA Fabric Transfer" section.
  • Changed the description of the Share reconfiguration interface parameter in the "Dynamic Reconfiguration" table.
2017.06.06 Made the following changes:
  • Removed QPI options from the "TX PMA Options" table.
  • Added the "PMA Functions" section.
  • Added the "Debug Functions" section.
  • Removed the Enable feedback compensation bonding parameter from the "fPLL IP Core Parameter Settings for PIPE" section.
  • Removed the Enable feedback compensation bonding parameter from the "ATX PLL IP Core Parameter Settings for PIPE" section.
  • Changed the parameter name, Store current configuration to profile, to match the GUI in the "Configuration Profiles" table.
  • Changed the figures in the "How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes" section.
  • Added the "Standard PCS Options" table.
  • Changed the logical PCS master channel number for the x1 PIPE configuration in the "Logical PCS Master Channel for PIPE Configuration" table.
  • Changed the values for Pre-Emphasis First Pre-Tap Magnitude and Pre-Emphasis First Post -Tap Magnitude in the "TX Analog PMA Settings Options" table.
  • Updated some parameters and descriptions in the "General, Common PMA Options, and Datapath Options" table.
  • Removed the Selected TX PCS bonding clock network parameter from the "TX Clock Options" table.
  • Removed the VGA Half BW Enable parameter from the "RX Analog PMA Settings" table.
  • Changed the name of the parameters in the "Byte Serializer and Deserializer Parameters" table to match the GUI.
  • Changed the description for rx_bitslip[<n>-1:0] in the "Gearbox" table.
  • Added the "Setting RX PMA Adaptation Modes" section.
  • Added the "Word Aligner in Deterministic Latency Mode for CPRI" section.
  • Removed the Best Case column from the "Register Chain Minimum Hold Time Calculations" table.
  • Removed the Best Case row from the "Register Chain Minimum Hold Time Calculations" table.
  • Updated the list of ports in the "PRBS Control and Status Ports" section.
  • Added the "PRBS Soft Accumulators Use Model" section.
2017.03.08 Made the following changes:
  • Changed the description of VGA Half BW Enable in the "RX Analog PMA Settings Options" table.
2017.02.17 Made the following changes:
  • Added the "GXT Channels" section.
  • Added the "Reconfiguring Between GX and GXT Channels" section.
  • Changed the description for the Enable rx_pma_clkslip port option in the "RX PMA Optional Ports" table.
  • Changed the list options for TX and RX analog PMA settings in the "Analog PMA Settings Parameters" section.
  • Removed parameters from the "TX Analog PMA Settings Options" and "RX Analog PMA Settings Options" tables.
  • Removed the "TX PMA Optional Ports - PMA QPI Options" table.
  • Changed the description for the rx_pma_clkslip port in the "RX PMA Ports" table.
  • Added the Enable PCS reset status ports option in the "PCS-Core Interface Parameters" table.
  • Added the "Implementing the PHY Layer for Transceiver Protocols" section.
2016.12.21 Initial release.
Level Two Title