3.1.1.5. ATX PLL IP Core - Parameters, Settings, and Ports

L- and H-Tile Transceiver PHY User Guide

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Date 1/30/2024

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3.1.1.5. ATX PLL IP Core - Parameters, Settings, and Ports

Table 127. ATX PLL IP Core - Configuration Options, Parameters, and Settings
Parameter	Range	Description
Message level for rule violations	Error	Specifies the messaging level to use for parameter rule violations. Error—Causes all rule violations to prevent IP generation.
Protocol mode	Basic PCIe Gen1 PCIe Gen2 PCIe Gen3 SDI_cascade OTN_cascade	Governs the internal setting rules for the VCO. This parameter is not a preset. You must set all other parameters for your protocol. SDI_cascade and OTN_cascade are supported cascade mode configurations and enables "ATX to FPLL cascade output port", "manual configuration of counters" and "fractional mode". Protocol mode SDI_cascade enables SDI cascade rule checks and OTN_cascade enables OTN cascade rule checks.
Bandwidth	Low Medium High	Specifies the VCO bandwidth. Higher bandwidth reduces PLL lock time, at the expense of decreased jitter rejection.
Number of PLL reference clocks	1 to 5	Specifies the number of input reference clocks for the ATX PLL. You can use this parameter for data rate reconfiguration.
Selected reference clock source	0 to 4	Specifies the initially selected reference clock input to the ATX PLL.
VCCR_GXB and VCCT_GXB supply voltage for the Transceiver	1_0V, and 1_1V ⁴⁴	Selects the VCCR_GXB and VCCT_GXB supply voltage for the Transceiver.
Primary PLL clock output buffer	GX clock output buffer/GXT clock output buffer	Specifies which PLL output is active initially. If GX is selected "Enable PLL GX clock output port" should be enabled. If GXT is selected "Enable PLL GXT clock output port" should be enabled.
Enable GX clock output port (tx_serial_clk)	On/Off	GX clock output port feeds x1 clock lines. Must be selected for PLL output frequency smaller than 8.7 GHz. If GX is selected in "Primary PLL clock output buffer", the port should be enabled as well.
Enable GXT clock output port to above ATX PLL (gxt_output_to_abv_atx)	On/Off	GXT clock output to above ATX PLL to feed the dedicated high speed clock lines. Must be selected for PLL output frequency greater than 8.7 GHz. If GXT is selected in "Primary PLL clock output buffer", the port should be enabled as well.
Enable GXT clock output port to below ATX PLL (gxt_output_to_blw_atx)	On/Off	GXT clock output to below ATX PLL to feed the dedicated high speed clock lines. Must be selected for PLL output frequency greater than 8.7 GHz. If GXT is selected in "Primary PLL clock output buffer", the port should be enabled as well.
Enable GXT local clock output port (tx_serial_clk_gxt)	Off	GXT local clock output port to feed the dedicated high speed clock lines. Must be selected for PLL output frequency greater than 8.7 GHz. If GXT is selected in "Primary PLL clock output buffer", the port should be enabled as well.
Enable GXT clock input port from above ATX PLL (gxt_input_from_abv_atx)	On/Off	GXT clock input port from Above ATX PLL port to drive the dedicated high speed clock lines. Must be selected for PLL input frequency greater than 8.7 GHz. If GXT is selected in "Primary PLL clock input buffer", the port should be enabled as well.
Enable GXT clock input port from below ATX PLL (gxt_input_from_blw_atx)	On/Off	GXT clock input port from Below ATX PLL port to drive the dedicated high speed clock lines. Must be selected for PLL input frequency greater than 8.7 GHz. If GXT is selected in "Primary PLL clock input buffer", the port should be enabled as well.
Enable PCIe clock output port	On/Off	This is the 500 MHz fixed PCIe clock output port and is intended for PIPE mode. The port should be connected to "pipe_hclk_in" port of the Native PHY IP.
Enable ATX to FPLL cascade clock output port	On/Off	Enables the ATX to FPLL cascade clock output port. This option selects Fractional mode and "Configure counters manually" option. OTN_cascade protocol mode enables OTN rule checks and SDI_cascade mode enables SDI rule checks
Enable GXT clock buffer to above ATX PLL	On/Off	GXT clock output port to drive the above ATX PLL. Must be selected for output frequency greater than 8.7 GHz. If GXT is selected in "Primary PLL clock input buffer", the port should be enabled as well.
Enable GXT clock buffer to below ATX PLL	On/Off	GXT clock output port to drive the below ATX PLL. Must be selected for output frequency greater than 8.7 GHz. If GXT is selected in "Primary PLL clock input buffer", the port should be enabled as well.
GXT output clock source	Local ATX PLL Input from ATX PLL above (gxt_input_from_abv_atx) Input from ATX PLL above (gxt_input_from_blw_atx) Disabled	Specifies which GXT clock output is active based on GXT 3:1 mux selection. The possible options are input from above/below ATX PLLs OR local ATX PLL.
PLL output frequency	Refer to the Transceiver Performance Specifications section of the Intel® Stratix® 10 Device Datasheet	Use this parameter to specify the target output frequency for the PLL.
PLL output datarate	Refer to the GUI	Specifies the target datarate for which the PLL is used.
PLL auto mode reference clock frequency (Integer)	Refer to the GUI	Selects the auto mode input reference clock frequency for the PLL (Integer).
Configure counters manually	On/Off	Enables manual control of PLL counters. Available only in ATX to FPLL cascade configuration
Multiply factor (M-Counter)	Read only For OTN_cascade or SDI_cascade, refer to the GUI	Displays the M-counter value. Specifies the M-counter value (In SDI_cascade or OTN_cascade Protocol mode only).
Divide factor (N-Counter)	Read only For SDI_cascade or OTN_cascade, refer to the GUI	Displays the N-counter value. For SDI_cascade or OTN_cascade, refer to the GUI.
Divide factor (L-Counter)	Read only	Displays the L-counter value.

Table 128. ATX PLL IP Core - Master Clock Generation Block Parameters and Settings
Parameter	Range	Description
Include Master Clock Generation Block ⁴⁵	On/Off	When enabled, includes a master CGB as a part of the ATX PLL IP core. The PLL output drives the Master CGB. This is used for x6/x24 bonded and non-bonded modes.
Clock division factor	1, 2, 4, 8	Divides the master CGB clock input before generating bonding clocks.
Enable x24 non-bonded high-speed clock output port	On/Off	Enables the master CGB serial clock output port used for x24 non-bonded modes.
Enable PCIe clock switch interface	On/Off	Enables the control signals for the PCIe clock switch circuitry. Used for PCIe clock rate switching.
Enable mcgb_rst and mcgb_rst_stat ports	On/Off	Enables the `mcgb_rst` and `mcgb_rst_stat` ports. These ports must be disabled for all PCIe configurations when using L-Tile or H-Tile devices.
Number of auxiliary MCGB clock input ports	0, 1	Auxiliary input is used to implement the PCIe Gen3 PIPE protocol. It is not available in fPLL.
MCGB input clock frequency	Read only	Displays the master CGB's input clock frequency. This parameter is not settable by user.
MCGB output data rate.	Read only	Displays the master CGB's output data rate. This parameter is not settable by user. The value is calculated based on "MCGB input clock frequency" and "Master CGB clock division factor".
Enable bonding clock output ports	On/Off	Enables the tx_bonding_clocks output ports of the master CGB used for channel bonding. This option should be turned ON for bonded designs.
PMA interface width	8, 10, 16, 20, 32, 40, 64	Specifies PMA-PCS interface width. Match this value with the PMA interface width selected for the Native PHY IP core. You must select a proper value for generating bonding clocks for the Native PHY IP core.

Table 129. ATX PLL IP Core - Dynamic Reconfiguration
Parameter	Range	Description
Enable dynamic reconfiguration	On/Off	Enables the dynamic reconfiguration interface.
Enable Native PHY Debug Master Endpoint	On/Off	When enabled, the PLL IP includes an embedded Native PHY Debug Master Endpoint that connects internally Avalon® memory-mapped interface slave. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the "Share reconfiguration interface" option for configurations using more than 1 channel and may also require that a `jtag_debug` link be included in the system.
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE	On/Off	When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.
Enable capability registers	On/Off	Enables capability registers, which provide high level information about the transceiver PLL's configuration.
Set user-defined IP identifier	0 to 255	Sets a user-defined numeric identifier that can be read from the user_identifer offset when the capability registers are enabled.
Enable control and status registers	On/Off	Enables soft registers for reading status signals and writing control signals on the phy interface through the embedded debug. Available signals include `pll_cal_busy`, pll_locked and pll_powerdown.
Configuration file prefix	altera_xcvr_atx_pll_s10	Specifies the file prefix to use for generated configuration files when enabled. Each variant of the IP should use a unique prefix for configuration files.
Generate SystemVerilog package file	On/Off	When enabled, the IP generates a SystemVerilog package file named "(Configuration file prefix)_reconfig_parameters.sv" containing parameters defined with the attribute values needed for reconfiguration.
Generate C header file	On/Off	When enabled, the IP generates a C header file named "(Configuration file prefix)_reconfig_parameters.h" containing macros defined with the attribute values needed for reconfiguration.
Generate MIF (Memory Initialize File)	On/Off	When enabled, the IP generates an MIF (Memory Initialization File) named "(Configuration file prefix)_reconfig_parameters.mif". The MIF file contains the attribute values needed for reconfiguration in a data format.
Enable multiple reconfiguration profiles	On/Off	When enabled, you can use the GUI to store multiple configurations. The IP generates reconfiguration files for all of the stored profiles. The IP also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them.
Enable embedded reconfiguration streamer	On/Off	Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles.
Generate reduced reconfiguration files	On/Off	When enabled, the Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles.
Number of reconfiguration profiles	1 to 8	Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Store current configuration to profile:	0 to 7	Selects which reconfiguration profile to store when clicking the "Store profile" button.

Table 130. ATX PLL IP Core - Ports
Port	Direction	Clock Domain	Description
`pll_refclk0`	Input	N/A	Reference clock input port 0. There are a total of five reference clock input ports. The number of reference clock ports available depends on the Number of PLL reference clocks parameter.
`pll_refclk1`	Input	N/A	Reference clock input port 1.
`pll_refclk2`	Input	N/A	Reference clock input port 2.
`pll_refclk3`	Input	N/A	Reference clock input port 3.
`pll_refclk4`	Input	N/A	Reference clock input port 4.
`mcgb_aux_clk0`	Input	N/A	Used for PCIe implementation to switch between fPLL and ATX PLL during link speed negotiation.
`pcie_sw[1:0]`	Input	Asynchronous	2-bit rate switch control input used for PCIe protocol implementation.
`gxt_input_from_abv_atx`	Input	N/A	GXT clock input from above ATX PLL to drive the dedicated high speed clock lines.
`gxt_input_from_blw_atx`	Input	N/A	GXT clock input from below ATX PLL to drive the dedicated high speed clock lines.
`mcgb_rst`	Input	N/A	Resets the master CGB. This port must be disabled for all PCIe configurations when using L-Tile or H-Tile devices.
`tx_serial_clk`	Output	N/A	High speed serial clock output port for GX channels. Represents the x1 clock network.
`pll_locked`	Output	Asynchronous	Active high status signal which indicates if the PLL is locked. When SDI_cascade or OTN_cascade protocol mode is selected, the `pll_locked` signal from the ATX PLL does not indicate the ATX PLL lock status. Refer to the downstream fPLL lock signal to indicate if both ATX and fPLL are locked. Note: The `pll_locked` signal should not be used when the ATX PLL IP is configured as a GXT clock buffer ATX PLL.
`pll_pcie_clk`	Output	N/A	Used for PCIe.
`pll_cal_busy`	Output	Asynchronous	Status signal which is asserted high when PLL calibration is in progress. OR this signal with tx_cal_busy port before connecting to the reset controller IP. Note: The `pll_cal_busy` signal should not be used when the ATX PLL IP is configured as a GXT clock buffer ATX PLL.
`tx_bonding_clocks[5:0]`	Output	N/A	Optional 6-bit bus which carries the low speed parallel clock outputs from the master CGB. Each transceiver channel in a bonded group has this 6-bit bus. Used for channel bonding, and represents the x6/x24 clock network.
`mcgb_serial_clk`	Output	N/A	High speed serial clock output for x6/x24 non-bonded configurations.
`pcie_sw_done[1:0]`	Output	Asynchronous	2-bit rate switch status output used for PCIe protocol implementation.
`atx_to_fpll_cascade_clk`	Output	N/A	The ATX PLL output clock is used to drive fPLL reference clock input (only available in SDI_cascade or OTN_cascade protocol mode).
`tx_serial_clk_gxt`	Output	N/A	GXT clock output to drive the dedicated high speed clock lines.
`gxt_output_to_abv_atx`	Output	N/A	GXT clock output to above ATX PLL to drive the dedicated high speed clock lines.
`gxt_output_to_blw_atx`	Output	N/A	GXT clock output to below ATX PLL to drive the dedicated high speed clock lines.
`mcgb_rst_stat`	Output	N/A	Status signal for the master CGB. This port must be disabled for all PCIe configurations when using L-Tile or H-Tile devices.

⁴⁴ Refer to the Intel® Stratix® 10 Device Datasheet for details about the minimum, typical, and maximum supply voltage specifications.

⁴⁵ Manually enable the MCGB for bonding applications.

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L- and H-Tile Transceiver PHY User Guide

3.1.1.5. ATX PLL IP Core - Parameters, Settings, and Ports