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1. Simultaneous Switching Noise (SSN) Analysis and Optimizations
2. Signal Integrity Analysis with Third-Party Tools
3. Mentor Graphics* PCB Design Tools Support
4. Cadence PCB Design Tools Support
5. Reviewing Printed Circuit Board Schematics with the Intel® Quartus® Prime Software
A. Intel® Quartus® Prime Standard Edition User Guides
1.1. Simultaneous Switching Noise (SSN) Analysis and Optimizations
1.2. Definitions
1.3. Understanding SSN
1.4. SSN Estimation Tools
1.5. SSN Analysis Overview
1.6. Design Factors Affecting SSN Results
1.7. Optimizing Your Design for SSN Analysis
1.8. Performing SSN Analysis and Viewing Results
1.9. Decreasing Processing Time for SSN Analysis
1.10. Scripting Support
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1.7.1. Optimizing Pin Placements for Signal Integrity
1.7.2. Specifying Board Trace Model Settings
1.7.3. Defining PCB Layers and PCB Layer Thickness
1.7.4. Specifying Signal Breakout Layers
1.7.5. Creating I/O Assignments
1.7.6. Decreasing Pessimism in SSN Analysis
1.7.7. Excluding Pins as Aggressor Signals
2.1. Signal Integrity Analysis with Third-Party Tools
2.2. I/O Model Selection: IBIS or HSPICE
2.3. FPGA to Board Signal Integrity Analysis Flow
2.4. Simulation with IBIS Models
2.5. Simulation with HSPICE Models
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2.4.1. Elements of an IBIS Model
2.4.2. Creating Accurate IBIS Models
2.4.3. Design Simulation Using the Mentor Graphics* HyperLynx* Software
2.4.4. Configuring LineSim to Use Intel IBIS Models
2.4.5. Integrating Intel IBIS Models into LineSim Simulations
2.4.6. Running and Interpreting LineSim Simulations
2.5.1. Supported Devices and Signaling
2.5.2. Accessing HSPICE Simulation Kits
2.5.3. The Double Counting Problem in HSPICE Simulations
2.5.4. HSPICE Writer Tool Flow
2.5.5. Running an HSPICE Simulation
2.5.6. Interpreting the Results of an Output Simulation
2.5.7. Interpreting the Results of an Input Simulation
2.5.8. Viewing and Interpreting Tabular Simulation Results
2.5.9. Viewing Graphical Simulation Results
2.5.10. Making Design Adjustments Based on HSPICE Simulations
2.5.11. Sample Input for I/O HSPICE Simulation Deck
2.5.12. Sample Output for I/O HSPICE Simulation Deck
2.5.13. Advanced Topics
2.5.4.1. Applying I/O Assignments
2.5.4.2. Enabling HSPICE Writer
2.5.4.3. Enabling HSPICE Writer Using Assignments
2.5.4.4. Naming Conventions for HSPICE Files
2.5.4.5. Invoking HSPICE Writer
2.5.4.6. Invoking HSPICE Writer from the Command Line
2.5.4.7. Customizing Automatically Generated HSPICE Decks
2.5.12.1. Header Comment
2.5.12.2. Simulation Conditions
2.5.12.3. Simulation Options
2.5.12.4. Constant Definition
2.5.12.5. I/O Buffer Netlist
2.5.12.6. Drive Strength
2.5.12.7. Slew Rate and Delay Chain
2.5.12.8. I/O Buffer Instantiation
2.5.12.9. Board and Trace Termination
2.5.12.10. Double-Counting Compensation Circuitry
2.5.12.11. Simulation Analysis
3.1. FPGA-to-PCB Design Flow
3.2. Integrating with I/O Designer
3.3. Integrating with DxDesigner
3.4. Analyzing FPGA Simultaneous Switching Noise (SSN)
3.5. Scripting API
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3.2.1. Generating Pin Assignment Files
3.2.2. I/O Designer Settings
3.2.3. Transferring I/O Assignments
3.2.4. Updating I/O Designer with Intel® Quartus® Prime Pin Assignments
3.2.5. Updating Intel® Quartus® Prime with I/O Designer Pin Assignments
3.2.6. Generating Schematic Symbols in I/O Designer
3.2.7. Exporting Schematic Symbols to DxDesigner
4.1. Cadence PCB Design Tools Support
4.2. Product Comparison
4.3. FPGA-to-PCB Design Flow
4.4. Setting Up the Intel® Quartus® Prime Software
4.5. FPGA-to-Board Integration with the Cadence Allegro Design Entry HDL Software
4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software
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5.1. Reviewing Intel® Quartus® Prime Software Settings
5.2. Reviewing Device Pin-Out Information in the Fitter Report
5.3. Reviewing Compilation Error and Warning Messages
5.4. Using Additional Intel® Quartus® Prime Software Features
5.5. Using Additional Intel® Quartus® Prime Software Tools
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4.6. FPGA-to-Board Integration with Cadence Allegro Design Entry CIS Software
The Cadence Allegro Design Entry CIS software is a schematic capture tool (part of the Cadence 200 series design flow based on OrCAD Capture CIS). Use the Cadence Allegro Design Entry CIS software to create flat circuit schematics for all types of PCB design. You can also create hierarchical schematics to facilitate design reuse and team-based design using the Cadence Allegro Design Entry CIS software. With the Cadence Allegro Design Entry CIS software, the design flow from FPGA-to-board is unidirectional using only the .pin generated by the Intel® Quartus® Prime software. You can only make signal and pin assignment changes in the Intel® Quartus® Prime software. These changes reflect as updated symbols in a Cadence Allegro Design Entry CIS schematic project.
Figure 36. Design Flow with the Cadence Allegro Design Entry CIS Software
Note: Routing or pin assignment changes made in a board layout tool or a Cadence Allegro Design Entry CIS symbol cannot be back-annotated to the Intel® Quartus® Prime software.