Cyclone® V SX, ST and SE SoC Device Errata

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ID 683618
Date 9/25/2015
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Document Table of Contents x
1. Cyclone® V SX, ST and SE SoC Device Errata
1. Cyclone® V SX, ST and SE SoC Device Errata x
1.1. Intel® -Specific SoC Errata for Cyclone® V SX, ST, and SE SoC Devices 1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata 1.3. Revision History for Cyclone® V SX, ST, and SE SoC Device Errata
1.1. Intel® -Specific SoC Errata for Cyclone® V SX, ST, and SE SoC Devices x
1.1.1. Hard Processor System (HPS) 1.1.2. FPGA
1.1.1. Hard Processor System (HPS) x
1.1.1.1. EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric 1.1.1.2. Hard Processor System Level 2 Cache Error Correction Code 1.1.1.3. Hard Processor System PLL Lock Issue After Power-on Reset or Cold Reset Description Workaround Status 1.1.1.4. HPS TAP Controller Is Reset By Cold Reset 1.1.1.5. SPI Slave Output Signals Cannot Be Isolated When Routed to the HPS Pins
1.1.2. FPGA x
1.1.2.1. External Memory Interface (EMIF) Maximum Frequency Specification Updage 1.1.2.2. Fractional PLL Phase Alignment Error 1.1.2.3. Power Connection Recommendation for Cyclone® V SoC ES Devices 1.1.2.4. Configuration via Protocol (CvP) 1.1.2.5. Usermode High Icc 1.1.2.6. False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode 1.1.2.7. JTAG Programming Operation Issue
1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata x
1.2.1. Arm* Cortex* -A9 MPU 1.2.2. Arm* L2 Cache Controller 1.2.3. Arm* CoreSight PTM
1.2.1. Arm* Cortex* -A9 MPU x
1.2.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain 1.2.1.2. 775420: Particular Data Cache Maintenance Operation Which Aborts Might Lead to Deadlock 1.2.1.3. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock 1.2.1.4. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock 1.2.1.5. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption 1.2.1.6. 740657: Global Timer Can Send Two Interrupts for the Same Event 1.2.1.7. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary 1.2.1.8. 754322: Faulty MMU Translations Following ASID Switch 1.2.1.9. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory 1.2.1.10. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault 1.2.1.11. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation 1.2.1.12. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements 1.2.1.13. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue 1.2.1.14. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D 1.2.1.15. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface 1.2.1.16. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded 1.2.1.17. 751471: DBGPCSR Format Is Incorrect 1.2.1.18. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads 1.2.1.19. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store 1.2.1.20. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses 1.2.1.21. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP 1.2.1.22. 761321: MRC and MCR Are Not Counted in Event 0x68 1.2.1.23. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF 1.2.1.24. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value 1.2.1.25. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB 1.2.1.26. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock 1.2.1.27. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back 1.2.1.28. 782774: A Spurious Event 0x63 Can be Reported on an LDREX That is preceded by a Write to Strongly Ordered Memory Region
1.2.2. Arm* L2 Cache Controller x
1.2.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area 1.2.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23 1.2.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
1.2.3. Arm* CoreSight PTM x
1.2.3.1. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 1.2.3.2. 711668: Configuration Extension Register Has Wrong Value Status
1. Cyclone® V SX, ST and SE SoC Device Errata

1.1.1.3. Hard Processor System PLL Lock Issue After Power-on Reset or Cold Reset

Description

One or more of the PLLs in the hard processor system (HPS) of Cyclone V SoC devices can take a long time to lock after power-on reset or cold reset. This occurs when the clock select (CSEL) pins are set to 01, 10, or 11. Some peripherals clocked by the HPS PLLs may fail to operate properly. While this failure is rare, typical symptoms include:

  • The HPS hangs during the Boot ROM stage and is unable to proceed to the Preloader stage.
  • An intermittent SDRAM calibration error in the Preloader.

Workaround

These issues can be resolved by implementing the following changes:

  1. Connect the CSEL pins [1:0] to pull down resistors (4.7 kΩ to 10 kΩ) on the board to force the CSEL input to be 0.
  2. Download and install the appropriate SoCEDS patch for software version 13.1 or 14.0. Then, recompile the Preloader code.

To download and install the required SoCEDS patch for SoCEDS version 13.1 and 14.0, refer to KDB solution rd06202014. Software in the patch is integrated into SoCEDS version 14.0.1.

Selecting CSEL=00 causes the Boot ROM to bypass the PLLs on cold reset, instead using the external clock input (osc_1_clk) for the peripheral interfaces. Because the external clock is already stable, using it ensures the Preloader code loads properly from external Flash.

The software patch adds code to the Preloader, which locks the PLLs quickly, which in turn resolves the intermittent SDRAM calibration issue. It also loads a piece of code into the on-chip RAM to handle a warm reset. Clocks are handled differently depending on whether the reset is warm or cold.

Bypassing the PLLs after cold reset increases the boot time slightly because the external clock is slower than the Flash interface clock generated from the HPS peripheral PLL. Intel reserves the upper 4 KB of on-chip RAM for the warm boot code.

Note: Do not overwrite the content of the upper 4 KB of the address range in the on-chip RAM. If you need a smaller memory footprint for the code, file a service request using Intel® Premier Support.

The on-chip memory restriction can be eliminated entirely if the SoC warm and cold reset pins are tied together, or if the HPS boots from FPGA memory.

Status

Affects: All Cyclone® V SX, ST, and SE devices

Table 3.  Device and Revision FixedThis table identifies the fixed silicon by die revision for each device.
Device Revision without Fix Revision with Fix
5CSEA2 Rev B Rev C
5CSEA4 Rev B Rev C
5CSEA5 Rev C Rev D
5CSEA6 Rev C Rev D
5CSXC2 Rev B Rev C
5CSXC4 Rev B Rev C
5CSXC5 Rev C Rev D
5CSXC6 Rev C Rev D
5CSTD5 Rev C Rev D
5CSTD6 Rev C Rev D
Figure 2.  Intel Date Code Marking FormatThis figure shows the silicon revision as identified by the fourth letter of the lot ID.
Level Two Title