Cyclone® V SX, ST and SE SoC Device Errata

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ID 683618
Date 9/25/2015
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Document Table of Contents x
1. Cyclone® V SX, ST and SE SoC Device Errata
1. Cyclone® V SX, ST and SE SoC Device Errata x
1.1. Intel® -Specific SoC Errata for Cyclone® V SX, ST, and SE SoC Devices 1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata 1.3. Revision History for Cyclone® V SX, ST, and SE SoC Device Errata
1.1. Intel® -Specific SoC Errata for Cyclone® V SX, ST, and SE SoC Devices x
1.1.1. Hard Processor System (HPS) 1.1.2. FPGA
1.1.1. Hard Processor System (HPS) x
1.1.1.1. EMAC RMII PHY Interface is Only Supported Through the FPGA Fabric 1.1.1.2. Hard Processor System Level 2 Cache Error Correction Code 1.1.1.3. Hard Processor System PLL Lock Issue After Power-on Reset or Cold Reset 1.1.1.4. HPS TAP Controller Is Reset By Cold Reset 1.1.1.5. SPI Slave Output Signals Cannot Be Isolated When Routed to the HPS Pins
1.1.2. FPGA x
1.1.2.1. External Memory Interface (EMIF) Maximum Frequency Specification Updage 1.1.2.2. Fractional PLL Phase Alignment Error 1.1.2.3. Power Connection Recommendation for Cyclone® V SoC ES Devices 1.1.2.4. Configuration via Protocol (CvP) 1.1.2.5. Usermode High Icc 1.1.2.6. False Configuration Failure in Active Serial Multi-Device Configuration x1 Mode 1.1.2.7. JTAG Programming Operation Issue
1.2. Arm* Cortex* -A9 MPCore* and L2 Cache Errata x
1.2.1. Arm* Cortex* -A9 MPU 1.2.2. Arm* L2 Cache Controller 1.2.3. Arm* CoreSight PTM
1.2.1. Arm* Cortex* -A9 MPU x
1.2.1.1. 761319: Ordering of Read Accesses to the Same Memory Location Might Be Uncertain 1.2.1.2. 775420: Particular Data Cache Maintenance Operation Which Aborts Might Lead to Deadlock 1.2.1.3. 782772: Speculative Execution of LDREX or STREX Instruction After a Write to Strongly Ordered Memory Might Lead to Deadlock 1.2.1.4. 761320: Full Cache Line Writes to the Same Memory Region From Both Processors Might Cause Deadlock 1.2.1.5. 845369: Under Very Rare Timing Circumstances Transition into Streaming Mode Might Create Data Corruption 1.2.1.6. 740657: Global Timer Can Send Two Interrupts for the Same Event 1.2.1.7. 751476: Missed Watchpoint on the Second Part of an Unaligned Access Crossing a Page Boundary 1.2.1.8. 754322: Faulty MMU Translations Following ASID Switch 1.2.1.9. 764369: Data or Unified Cache Line Maintenance by MVA Fails on Inner-Shareable Memory 1.2.1.10. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault Description Impact Workaround Category 1.2.1.11. 794072: A Short Loop Including DMB Instruction Might Cause a Denial of Service When the Other Processor Executes a CP15 Broadcast Operation 1.2.1.12. 794073: Speculative Instruction Fetches with MMU Disabled Might Not Comply with Architectural Requirements 1.2.1.13. 794074: A Write Request to an Uncacheable, Shareable Normal Memory Region Might be Executed Twice, Possibly Causing a Software Synchronization Issue 1.2.1.14. 725631: ISB is Counted in Performance Monitor Events 0x0C and 0x0D 1.2.1.15. 729817: MainID Register Alias Addresses Are Not Mapped on Debug APB Interface 1.2.1.16. 729818: In Debug State, the Next Instruction is Stalled When the SDABORT Flag is Set Instead of Being Discarded 1.2.1.17. 751471: DBGPCSR Format Is Incorrect 1.2.1.18. 752519: An Imprecise Abort Might Be Reported Twice on Non-Cacheable Reads 1.2.1.19. 754323: Repeated Store in the Same Cache Line Might Delay the Visibility of the Store 1.2.1.20. 756421: Sticky Pipeline Advance Bit Cannot be Cleared from Debug APB Accesses 1.2.1.21. 757119: Some Unallocated Memory Hint Instructions Generate an UNDEFINED Exception Instead of Being Treated as a NOP 1.2.1.22. 761321: MRC and MCR Are Not Counted in Event 0x68 1.2.1.23. 764319: Read Accesses to DBGPRSR and DBGPRCR May Generate an Unexpected UNDEF 1.2.1.24. 771221: PLD Instructions Might Allocate Data in the Data Cache Regardless of the Cache Enable Bit Value 1.2.1.25. 771224: Visibility of Debug Enable Access Rights to Enable/Disable Tracking is Not Ensured by an ISB 1.2.1.26. 771225: Speculative Cacheable Reads to Aborting Memory Regions Clear the Internal Exclusive Monitor and May Lead to Livelock 1.2.1.27. 775419: PMU Event 0x0A Might Count Twice the LDM PC ^ Instruction with Base Address Register Write-Back 1.2.1.28. 782774: A Spurious Event 0x63 Can be Reported on an LDREX That is preceded by a Write to Strongly Ordered Memory Region
1.2.2. Arm* L2 Cache Controller x
1.2.2.1. 754670: A Continuous Write Flow Can Stall a Read Targeting the Same Memory Area 1.2.2.2. 765569: Prefetcher Can Cross 4 KB Boundary if Offset is Programmed with Value 23 1.2.2.3. 729815: The High Priority for SO and Dev Reads Feature Can Cause Quality of Service Issues to Cacheable Read Transactions
1.2.3. Arm* CoreSight PTM x
1.2.3.1. 720107: Periodic Synchronization Can Be Delayed and Cause Overflow 1.2.3.2. 711668: Configuration Extension Register Has Wrong Value Status
1. Cyclone® V SX, ST and SE SoC Device Errata

1.2.1.10. 782773: Updating a Translation Entry to Move a Page Mapping Might Erroneously Cause an Unexpected Translation Fault

Description

Under certain conditions specific to the Cortex* -A9 microarchitecture, a write operation that updates a cacheable translation table entry might cause both the old and the new translation entry to be temporarily invisible to translation table walks, thus erroneously causing a translation fault.

This erratum requires the following conditions to happen:

  1. The processor has its data cache and MMU enabled.
  2. The TTB registers are set to work on memory regions with cacheable descriptors.
  3. The processor is updating an existing cacheable translation table entry, and this write operation hits in the L1 data cache.
  4. A hardware translation table walk is attempted. The hardware translation table walk can be due to either an instruction fetch, or to any other instruction execution that requires an address translation, including any load or store operation. This hardware translation walk must attempt to access the entry being updated in condition 2, and that access must hit in the L1 data cache.

In practice, this scenario can happen when an OS is changing the mapping of a physical page. The OS might have an existing mapping to a physical page (the old mapping), but wants to move the mapping to a new page (the new mapping). To do this, the OS might:

  • Write a new translation entry, without cancelling the old one. At this point, the physical page is accessible using either the old mapping or the new mapping.
  • Execute a DSB instruction followed by an ISB instruction pair, to ensure that the new translation entry is fully visible.
  • Remove the old entry.

Because of this erratum, this sequence might fail because it can happen that neither the new mapping, nor the old mapping, is visible after the new entry is written, causing a translation fault.

Impact

This erratum causes a translation fault.

Workaround

The recommended workaround is to perform a clean and invalidate operation on the cache line that contains the translation entry before updating the entry, to ensure that the write operation misses in the data cache. This workaround prevents the microarchitectural conditions for this erratum from happening. Interrupts must be temporarily disabled so that no interrupt can be taken between the maintenance operation and the translation entry update to avoid the possibility of the interrupt service routine bringing the cache line back in the cache.

Another possible workaround is to place the translation table entries in non-cacheable memory areas, but this workaround is likely to have a noticeable performance penalty. Note that inserting a DSB instruction immediately after writing the new translation table entry significantly reduces the probability of encountering this erratum, but is not a complete workaround.

Category

Category 3

Level Two Title