Arria® 10 Transceiver PHY User Guide

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ID 683617
Date 4/01/2024
Public
Document Table of Contents
Document Table of Contents x
1. Arria® 10 Transceiver PHY Overview 2. Implementing Protocols in Arria 10 Transceivers 3. PLLs and Clock Networks 4. Resetting Transceiver Channels 5. Arria 10 Transceiver PHY Architecture 6. Reconfiguration Interface and Dynamic Reconfiguration 7. Calibration 8. Analog Parameter Settings 9. Debugging Transceiver Toolkit
1. Arria® 10 Transceiver PHY Overview x
1.1. Device Transceiver Layout 1.2. Transceiver PHY Architecture Overview 1.3. Calibration 1.4. Arria® 10 Transceiver PHY Overview Revision History
1.1. Device Transceiver Layout x
1.1.1. Arria® 10 GX Device Transceiver Layout 1.1.2. Arria® 10 GT Device Transceiver Layout 1.1.3. Arria® 10 GX and GT Device Package Details 1.1.4. Arria® 10 SX Device Transceiver Layout 1.1.5. Arria® 10 SX Device Package Details
1.2. Transceiver PHY Architecture Overview x
1.2.1. Transceiver Bank Architecture 1.2.2. PHY Layer Transceiver Components 1.2.3. Transceiver Phase-Locked Loops 1.2.4. Clock Generation Block (CGB)
1.2.2. PHY Layer Transceiver Components x
1.2.2.1. The GX Transceiver Channel 1.2.2.2. The GT Transceiver Channel
1.2.3. Transceiver Phase-Locked Loops x
1.2.3.1. Advanced Transmit (ATX) PLL 1.2.3.2. Fractional PLL (fPLL) 1.2.3.3. Channel PLL (CMU/CDR PLL)
2. Implementing Protocols in Arria 10 Transceivers x
2.1. Transceiver Design IP Blocks 2.2. Transceiver Design Flow 2.3. Arria® 10 Transceiver Protocols and PHY IP Support 2.4. Using the Arria® 10 Transceiver Native PHY IP Core 2.5. Interlaken 2.6. Ethernet 2.7. PCI Express* (PIPE) 2.8. CPRI 2.9. Other Protocols 2.10. Simulating the Transceiver Native PHY IP Core 2.11. Implementing Protocols in Arria® 10 Transceivers Revision History
2.2. Transceiver Design Flow x
2.2.1. Select and Instantiate the PHY IP Core 2.2.2. Configure the PHY IP Core 2.2.3. Generate the PHY IP Core 2.2.4. Select the PLL IP Core 2.2.5. Configure the PLL IP Core 2.2.6. Generate the PLL IP Core 2.2.7. Reset Controller 2.2.8. Create Reconfiguration Logic 2.2.9. Connect the PHY IP to the PLL IP Core and Reset Controller 2.2.10. Connect Datapath 2.2.11. Make Analog Parameter Settings 2.2.12. Compile the Design 2.2.13. Verify Design Functionality
2.4. Using the Arria® 10 Transceiver Native PHY IP Core x
2.4.1. Presets 2.4.2. General and Datapath Parameters 2.4.3. PMA Parameters 2.4.4. Enhanced PCS Parameters 2.4.5. Standard PCS Parameters 2.4.6. PCS Direct 2.4.7. Dynamic Reconfiguration Parameters 2.4.8. PMA Ports 2.4.9. Enhanced PCS Ports 2.4.10. Standard PCS Ports 2.4.11. IP Core File Locations 2.4.12. Unused Transceiver RX Channels 2.4.13. Unsupported Features
2.4.9. Enhanced PCS Ports x
2.4.9.1. Enhanced PCS TX and RX Control Ports
2.5. Interlaken x
2.5.1. Metaframe Format and Framing Layer Control Word 2.5.2. Interlaken Configuration Clocking and Bonding 2.5.3. How to Implement Interlaken in Arria 10 Transceivers 2.5.4. Design Example 2.5.5. Native PHY IP Parameter Settings for Interlaken
2.5.2. Interlaken Configuration Clocking and Bonding x
2.5.2.1. xN Clock Bonding Scenario 2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine
2.5.2.2. TX Multi-Lane Bonding and RX Multi-Lane Deskew Alignment State Machine x
2.5.2.2.1. TX FIFO Soft Bonding 2.5.2.2.2. RX Multi-lane FIFO Deskew State Machine
2.6. Ethernet x
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants 2.6.3. 10GBASE-KR PHY IP Core 2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core 2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.6. XAUI PHY IP Core 2.6.7. Acronyms
2.6.1. Gigabit Ethernet (GbE) and GbE with IEEE 1588v2 x
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 2.6.1.2. Word Alignment for GbE, GbE with IEEE 1588v2 2.6.1.3. 8B/10B Decoding for GbE, GbE with IEEE 1588v2 2.6.1.4. Rate Match FIFO for GbE 2.6.1.5. How to Implement GbE, GbE with IEEE 1588v2 in Arria® 10 Transceivers 2.6.1.6. Native PHY IP Parameter Settings for GbE and GbE with IEEE 1588v2
2.6.1.1. 8B/10B Encoding for GbE, GbE with IEEE 1588v2 x
2.6.1.1.1. Reset Condition for 8B/10B Encoder in GbE, GbE with IEEE 1588v2
2.6.2. 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC Variants x
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R 2.6.2.2. How to Implement 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC in Arria 10 Transceivers 2.6.2.3. Native PHY IP Parameter Settings for 10GBASE-R, 10GBASE-R with IEEE 1588v2, and 10GBASE-R with FEC 2.6.2.4. Native PHY IP Ports for 10GBASE-R and 10GBASE-R with IEEE 1588v2 Transceiver Configurations
2.6.2.1. The XGMII Clocking Scheme in 10GBASE-R x
2.6.2.1.1. TX FIFO and RX FIFO
2.6.3. 10GBASE-KR PHY IP Core x
2.6.3.1. 10GBASE-KR PHY Release Information 2.6.3.2. 10GBASE-KR PHY Performance and Resource Utilization 2.6.3.3. 10GBASE-KR Functional Description 2.6.3.4. Parameterizing the 10GBASE-KR PHY 2.6.3.5. 10GBASE-KR PHY Interfaces 2.6.3.6. Avalon® Memory-Mapped Interface Registers 2.6.3.7. Creating a 10GBASE-KR Design 2.6.3.8. Design Example 2.6.3.9. Simulation Support
2.6.3.4. Parameterizing the 10GBASE-KR PHY x
2.6.3.4.1. General Options 2.6.3.4.2. 10GBASE-R Parameters 2.6.3.4.3. 10GBASE-KR Auto-Negotiation and Link Training Parameters 2.6.3.4.4. 10GBASE-KR Optional Parameters 2.6.3.4.5. Speed Detection Parameters
2.6.3.5. 10GBASE-KR PHY Interfaces x
2.6.3.5.1. Clock and Reset Interfaces 2.6.3.5.2. Data Interfaces 2.6.3.5.3. XGMII Mapping to Standard SDR XGMII Data 2.6.3.5.4. Serial Data Interface 2.6.3.5.5. Control and Status Interfaces 2.6.3.5.6. Dynamic Reconfiguration Interface
2.6.3.6. Avalon® Memory-Mapped Interface Registers x
2.6.3.6.1. 10GBASE-KR PHY Register Definitions 2.6.3.6.2. Hard Transceiver PHY Registers 2.6.3.6.3. Enhanced PCS Registers 2.6.3.6.4. PMA Registers
2.6.4. 1-Gigabit/10-Gigabit Ethernet (GbE) PHY IP Core x
2.6.4.1. 1G/10GbE PHY Release Information 2.6.4.2. 1G/10GbE PHY Performance and Resource Utilization 2.6.4.3. 1G/10GbE PHY Functional Description 2.6.4.4. Clock and Reset Interfaces 2.6.4.5. Parameterizing the 1G/10GbE PHY 2.6.4.6. 1G/10GbE PHY Interfaces 2.6.4.7. Avalon® Memory-Mapped Interface Registers 2.6.4.8. Creating a 1G/10GbE Design 2.6.4.9. Design Guidelines 2.6.4.10. Channel Placement Guidelines 2.6.4.11. Design Example 2.6.4.12. Simulation Support 2.6.4.13. TimeQuest Timing Constraints
2.6.4.5. Parameterizing the 1G/10GbE PHY x
2.6.4.5.1. General Options 2.6.4.5.2. 10GBASE-R Parameters 2.6.4.5.3. 10M/100M/1Gb Ethernet Parameters 2.6.4.5.4. Speed Detection Parameters 2.6.4.5.5. PHY Analog Parameters
2.6.4.6. 1G/10GbE PHY Interfaces x
2.6.4.6.1. Clock and Reset Interfaces 2.6.4.6.2. Data Interfaces 2.6.4.6.3. XGMII Mapping to Standard SDR XGMII Data 2.6.4.6.4. GMII Interface 2.6.4.6.5. Serial Data Interface 2.6.4.6.6. Control and Status Interfaces 2.6.4.6.7. MII 2.6.4.6.8. Dynamic Reconfiguration Interface
2.6.4.7. Avalon® Memory-Mapped Interface Registers x
2.6.4.7.1. 1G/10GbE Register Definitions 2.6.4.7.2. Hard Transceiver PHY Registers 2.6.4.7.3. Enhanced PCS Registers 2.6.4.7.4. Arria 10 GMII PCS Registers 2.6.4.7.5. PMA Registers 2.6.4.7.6. Speed Change Summary
2.6.5. 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.5.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core 2.6.5.2. Using the IP Core 2.6.5.3. Functional Description 2.6.5.4. Configuration Registers 2.6.5.5. Interface Signals
2.6.5.1. About the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP Core x
2.6.5.1.1. Features 2.6.5.1.2. Release Information 2.6.5.1.3. Device Family Support 2.6.5.1.4. Resource Utilization
2.6.5.2. Using the IP Core x
2.6.5.2.1. Parameter Settings
2.6.5.3. Functional Description x
2.6.5.3.1. Clocking and Reset Sequence 2.6.5.3.2. Timing Constraints 2.6.5.3.3. Switching Operation Speed
2.6.5.4. Configuration Registers x
2.6.5.4.1. Register Map 2.6.5.4.2. Configuration Registers
2.6.5.5. Interface Signals x
2.6.5.5.1. Clock and Reset Signals 2.6.5.5.2. Operating Mode and Speed Signals 2.6.5.5.3. GMII Signals 2.6.5.5.4. XGMII Signals 2.6.5.5.5. Status Signals 2.6.5.5.6. Serial Interface Signals 2.6.5.5.7. Transceiver Status and Reconfiguration Signals 2.6.5.5.8. Avalon® Memory-Mapped Interface Signals
2.6.6. XAUI PHY IP Core x
2.6.6.1. Transceiver Datapath in a XAUI Configuration 2.6.6.2. XAUI Supported Features 2.6.6.3. XAUI PHY Release Information 2.6.6.4. XAUI PHY Device Family Support 2.6.6.5. Transceiver Clocking and Channel Placement Guidelines in XAUI Configuration 2.6.6.6. XAUI PHY Performance and Resource Utilization 2.6.6.7. Parameterizing the XAUI PHY 2.6.6.8. XAUI PHY Ports 2.6.6.9. XAUI PHY Interfaces 2.6.6.10. XAUI PHY Register Interface and Register Descriptions 2.6.6.11. XAUI PHY Timing Analyzer SDC Constraint
2.6.6.7. Parameterizing the XAUI PHY x
2.6.6.7.1. XAUI PHY General Parameters 2.6.6.7.2. XAUI PHY Advanced Options Parameters
2.6.6.9. XAUI PHY Interfaces x
2.6.6.9.1. SDR XGMII TX Interface 2.6.6.9.2. SDR XGMII RX Interface 2.6.6.9.3. Transceiver Serial Data Interface 2.6.6.9.4. XAUI PHY Clocks, Reset, and Powerdown Interfaces 2.6.6.9.5. XAUI PHY PMA Channel Controller Interface 2.6.6.9.6. XAUI PHY Optional PMA Control and Status Interface
2.7. PCI Express* (PIPE) x
2.7.1. Transceiver Channel Datapath for PIPE 2.7.2. Supported PIPE Features 2.7.3. How to Connect TX PLLs for PIPE Gen1, Gen2, and Gen3 Modes 2.7.4. How to Implement PCI Express* (PIPE) in Arria 10 Transceivers 2.7.5. Native PHY IP Parameter Settings for PIPE 2.7.6. fPLL IP Parameter Core Settings for PIPE 2.7.7. ATX PLL IP Parameter Core Settings for PIPE 2.7.8. Native PHY IP Ports for PIPE 2.7.9. fPLL Ports for PIPE 2.7.10. ATX PLL Ports for PIPE 2.7.11. Preset Mappings to TX De-emphasis 2.7.12. How to Place Channels for PIPE Configurations 2.7.13. PHY IP Core for PCIe* (PIPE) Link Equalization for Gen3 Data Rate 2.7.14. Using Transceiver Toolkit (TTK)/System Console/Reconfiguration Interface to manually tune Arria® 10 PCIe designs (Hard IP(HIP) and PIPE) (For debug only)
2.7.2. Supported PIPE Features x
2.7.2.1. Gen1/Gen2 Features 2.7.2.2. Gen3 Features
2.7.2.1. Gen1/Gen2 Features x
2.7.2.1.1. Dynamic Switching Between Gen1 (2.5 Gbps) and Gen2 (5 Gbps) 2.7.2.1.2. Transmitter Electrical Idle Generation 2.7.2.1.3. Power State Management 2.7.2.1.4. 8B/10B Encoder Usage for Compliance Pattern Transmission Support 2.7.2.1.5. Receiver Status 2.7.2.1.6. Receiver Detection 2.7.2.1.7. Gen1 and Gen2 Clock Compensation 2.7.2.1.8. PCIe* Reverse Parallel Loopback
2.7.2.2. Gen3 Features x
2.7.2.2.1. Auto-Speed Negotiation 2.7.2.2.2. Rate Switch 2.7.2.2.3. Gen3 Transmitter Electrical Idle Generation 2.7.2.2.4. Gen3 Clock Compensation 2.7.2.2.5. Gen3 Power State Management 2.7.2.2.6. CDR Control 2.7.2.2.7. Gearbox
2.7.12. How to Place Channels for PIPE Configurations x
2.7.12.1. Master Channel in Bonded Configurations
2.8. CPRI x
2.8.1. Transceiver Channel Datapath and Clocking for CPRI 2.8.2. Supported Features for CPRI 2.8.3. Word Aligner in Manual Mode for CPRI 2.8.4. How to Implement CPRI in Arria® 10 Transceivers 2.8.5. Native PHY IP Parameter Settings for CPRI
2.8.1. Transceiver Channel Datapath and Clocking for CPRI x
2.8.1.1. TX PLL Selection for CPRI 2.8.1.2. Auto-Negotiation
2.8.2. Supported Features for CPRI x
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI
2.8.2.1. Word Aligner in Deterministic Latency Mode for CPRI x
2.8.2.1.1. Transmitter and Receiver Latency
2.9. Other Protocols x
2.9.1. Using the 'Basic (Enhanced PCS)' and 'Basic with KR FEC' Configurations of Enhanced PCS 2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS 2.9.3. Design Considerations for Implementing Arria 10 GT Channels 2.9.4. How to Implement PCS Direct Transceiver Configuration Rule
2.9.1. Using the 'Basic (Enhanced PCS)' and 'Basic with KR FEC' Configurations of Enhanced PCS x
2.9.1.1. How to Implement the Basic (Enhanced PCS) and Basic with KR FEC Transceiver Configuration Rules in Arria 10 Transceivers 2.9.1.2. Native PHY IP Parameter Settings for Basic (Enhanced PCS) and Basic with KR FEC 2.9.1.3. How to Enable Low Latency in Basic Enhanced PCS 2.9.1.4. Enhanced PCS FIFO Operation 2.9.1.5. TX Data Bitslip 2.9.1.6. TX Data Polarity Inversion 2.9.1.7. RX Data Bitslip 2.9.1.8. RX Data Polarity Inversion
2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS x
2.9.2.1. Word Aligner Manual Mode 2.9.2.2. Word Aligner Synchronous State Machine Mode 2.9.2.3. RX Bit Slip 2.9.2.4. RX Polarity Inversion 2.9.2.5. RX Bit Reversal 2.9.2.6. RX Byte Reversal 2.9.2.7. Rate Match FIFO in Basic (Single Width) Mode 2.9.2.8. Rate Match FIFO Basic (Double Width) Mode 2.9.2.9. 8B/10B Encoder and Decoder 2.9.2.10. 8B/10B TX Disparity Control 2.9.2.11. How to Enable Low Latency in Basic 2.9.2.12. TX Bit Slip 2.9.2.13. TX Polarity Inversion 2.9.2.14. TX Bit Reversal 2.9.2.15. TX Byte Reversal 2.9.2.16. How to Implement the Basic, Basic with Rate Match Transceiver Configuration Rules in Arria® 10 Transceivers 2.9.2.17. Native PHY IP Parameter Settings for Basic, Basic with Rate Match Configurations
2.9.3. Design Considerations for Implementing Arria 10 GT Channels x
2.9.3.1. Transceiver PHY IP 2.9.3.2. PLL and GT Transceiver Channel Clock Lines 2.9.3.3. Reset Controller 2.9.3.4. How to Implement Designs for Data Rates Above 17.4 Gbps Using Enhanced PCS in Low Latency Mode 2.9.3.5. Arria 10 GT Channel Usage
2.10. Simulating the Transceiver Native PHY IP Core x
2.10.1. NativeLink Simulation Flow 2.10.2. Scripting IP Simulation 2.10.3. Custom Simulation Flow
2.10.1. NativeLink Simulation Flow x
2.10.1.1. How to Use NativeLink to Specify a ModelSim* Simulation 2.10.1.2. How to Use NativeLink to Run a ModelSim* RTL Simulation 2.10.1.3. How to Use NativeLink to Specify Third-Party RTL Simulators
2.10.2. Scripting IP Simulation x
2.10.2.1. Generating a Combined Simulator Setup Script
2.10.3. Custom Simulation Flow x
2.10.3.1. How to Use the Simulation Library Compiler 2.10.3.2. Custom Simulation Scripts
3. PLLs and Clock Networks x
3.1. PLLs 3.2. Input Reference Clock Sources 3.3. Transmitter Clock Network 3.4. Clock Generation Block 3.5. FPGA Fabric-Transceiver Interface Clocking 3.6. Transmitter Data Path Interface Clocking 3.7. Receiver Data Path Interface Clocking 3.8. Unused/Idle Clock Line Requirements 3.9. Channel Bonding 3.10. PLL Feedback and Cascading Clock Network 3.11. Using PLLs and Clock Networks 3.12. PLLs and Clock Networks Revision History
3.1. PLLs x
3.1.1. Transmit PLLs Spacing Guideline when using ATX PLLs and fPLLs 3.1.2. ATX PLL 3.1.3. fPLL 3.1.4. CMU PLL
3.1.2. ATX PLL x
3.1.2.1. Instantiating the ATX PLL IP Core 3.1.2.2. ATX PLL IP Core
3.1.3. fPLL x
3.1.3.1. Instantiating the fPLL IP Core 3.1.3.2. fPLL IP Core
3.1.4. CMU PLL x
3.1.4.1. Instantiating CMU PLL IP Core 3.1.4.2. CMU PLL IP Core
3.2. Input Reference Clock Sources x
3.2.1. Dedicated Reference Clock Pins 3.2.2. Receiver Input Pins 3.2.3. PLL Cascading as an Input Reference Clock Source 3.2.4. Reference Clock Network 3.2.5. Global Clock or Core Clock as an Input Reference Clock
3.3. Transmitter Clock Network x
3.3.1. x1 Clock Lines 3.3.2. x6 Clock Lines 3.3.3. xN Clock Lines 3.3.4. GT Clock Lines
3.9. Channel Bonding x
3.9.1. PMA Bonding 3.9.2. PMA and PCS Bonding 3.9.3. PCS Bonding Channels Placement Restrictions 3.9.4. Selecting Channel Bonding Schemes 3.9.5. Skew Calculations
3.9.1. PMA Bonding x
3.9.1.1. x6/xN Bonding 3.9.1.2. PLL Feedback Compensation Bonding
3.11. Using PLLs and Clock Networks x
3.11.1. Non-bonded Configurations 3.11.2. Bonded Configurations 3.11.3. Implementing PLL Cascading 3.11.4. Mix and Match Example 3.11.5. Timing Closure Recommendations
3.11.1. Non-bonded Configurations x
3.11.1.1. Implementing Single Channel x1 Non-Bonded Configuration 3.11.1.2. Implementing Multi-Channel x1 Non-Bonded Configuration 3.11.1.3. Implementing Multi-Channel xN Non-Bonded Configuration
3.11.2. Bonded Configurations x
3.11.2.1. Implementing x6/xN Bonding Mode 3.11.2.2. Implementing PLL Feedback Compensation Bonding Mode
4. Resetting Transceiver Channels x
4.1. When Is Reset Required? 4.2. Transceiver PHY Implementation 4.3. How Do I Reset? 4.4. Using the Transceiver PHY Reset Controller 4.5. Using a User-Coded Reset Controller 4.6. Combining Status or PLL Lock Signals 4.7. Timing Constraints for Bonded PCS and PMA Channels 4.8. Resetting Transceiver Channels Revision History
4.3. How Do I Reset? x
4.3.1. Model 1: Default Model 4.3.2. Model 2: Acknowledgment Model 4.3.3. Transceiver Blocks Affected by Reset and Powerdown Signals
4.3.1. Model 1: Default Model x
4.3.1.1. Recommended Reset Sequence 4.3.1.2. Resetting the Transmitter During Device Operation 4.3.1.3. Resetting the Receiver During Device Operation 4.3.1.4. Resetting the Transceiver Channel During Device Operation 4.3.1.5. Dynamic Reconfiguration of Channel Using the Default Model
4.3.2. Model 2: Acknowledgment Model x
4.3.2.1. Recommended Reset Sequence 4.3.2.2. Resetting the Transmitter During Device Operation 4.3.2.3. Resetting the Receiver During Device Operation 4.3.2.4. Dynamic Reconfiguration of Transmitter Channel Using the Acknowledgment Model 4.3.2.5. Dynamic Reconfiguration of Receiver Channel Using the Acknowledgment Model
4.4. Using the Transceiver PHY Reset Controller x
4.4.1. Parameterizing the Transceiver PHY Reset Controller IP 4.4.2. Transceiver PHY Reset Controller Parameters 4.4.3. Transceiver PHY Reset Controller Interfaces 4.4.4. Transceiver PHY Reset Controller Resource Utilization
4.5. Using a User-Coded Reset Controller x
4.5.1. User-Coded Reset Controller Signals
5. Arria 10 Transceiver PHY Architecture x
5.1. Arria® 10 PMA Architecture 5.2. Arria 10 Enhanced PCS Architecture 5.3. Arria® 10 Standard PCS Architecture 5.4. Arria 10 PCI Express* Gen3 PCS Architecture 5.5. Arria® 10 Transceiver PHY Architecture Revision History
5.1. Arria® 10 PMA Architecture x
5.1.1. Transmitter 5.1.2. Serializer 5.1.3. Transmitter Buffer 5.1.4. Receiver 5.1.5. Receiver Buffer 5.1.6. Clock Data Recovery (CDR) Unit 5.1.7. Deserializer 5.1.8. Loopback
5.1.3. Transmitter Buffer x
5.1.3.1. High Speed Differential I/O 5.1.3.2. Programmable Output Differential Voltage 5.1.3.3. Programmable Pre-Emphasis 5.1.3.4. Power Distribution Network (PDN) induced Inter-Symbol Interference (ISI) compensation 5.1.3.5. Programmable Transmitter On-Chip Termination (OCT)
5.1.5. Receiver Buffer x
5.1.5.1. Programmable Common Mode Voltage (VCM) 5.1.5.2. Programmable Differential On-Chip Termination (OCT) 5.1.5.3. Signal Detector 5.1.5.4. Continuous Time Linear Equalization (CTLE) 5.1.5.5. Variable Gain Amplifier (VGA) 5.1.5.6. Decision Feedback Equalization (DFE) 5.1.5.7. How to Enable CTLE and DFE
5.1.6. Clock Data Recovery (CDR) Unit x
5.1.6.1. Lock-to-Reference Mode 5.1.6.2. Lock-to-Data Mode 5.1.6.3. CDR Lock Modes
5.2. Arria 10 Enhanced PCS Architecture x
5.2.1. Transmitter Datapath 5.2.2. Receiver Datapath
5.2.1. Transmitter Datapath x
5.2.1.1. Enhanced PCS TX FIFO 5.2.1.2. Interlaken Frame Generator 5.2.1.3. Interlaken CRC-32 Generator 5.2.1.4. 64B/66B Encoder and Transmitter State Machine (TX SM) 5.2.1.5. Pattern Generators 5.2.1.6. Scrambler 5.2.1.7. Interlaken Disparity Generator 5.2.1.8. TX Gearbox, TX Bitslip and Polarity Inversion 5.2.1.9. KR FEC Blocks
5.2.1.1. Enhanced PCS TX FIFO x
5.2.1.1.1. Phase Compensation Mode 5.2.1.1.2. Register Mode 5.2.1.1.3. Interlaken Mode 5.2.1.1.4. Basic Mode
5.2.1.5. Pattern Generators x
5.2.1.5.1. PRBS Pattern Generator (Shared between Enhanced PCS and Standard PCS) 5.2.1.5.2. Pseudo-Random Pattern Generator
5.2.2. Receiver Datapath x
5.2.2.1. RX Gearbox, RX Bitslip, and Polarity Inversion 5.2.2.2. Block Synchronizer 5.2.2.3. Interlaken Disparity Checker 5.2.2.4. Descrambler 5.2.2.5. Interlaken Frame Synchronizer 5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) 5.2.2.7. Pseudo Random Pattern Verifier 5.2.2.8. 10GBASE-R Bit-Error Rate (BER) Checker 5.2.2.9. Interlaken CRC-32 Checker 5.2.2.10. Enhanced PCS RX FIFO 5.2.2.11. RX KR FEC Blocks
5.2.2.6. 64B/66B Decoder and Receiver State Machine (RX SM) x
5.2.2.6.1. PRBS Checker
5.2.2.10. Enhanced PCS RX FIFO x
5.2.2.10.1. Phase Compensation Mode 5.2.2.10.2. Register Mode 5.2.2.10.3. Interlaken Mode 5.2.2.10.4. 10GBASE-R Mode 5.2.2.10.5. Basic Mode
5.3. Arria® 10 Standard PCS Architecture x
5.3.1. Transmitter Datapath 5.3.2. Receiver Datapath
5.3.1. Transmitter Datapath x
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) 5.3.1.2. Byte Serializer 5.3.1.3. 8B/10B Encoder 5.3.1.4. Polarity Inversion Feature 5.3.1.5. Pseudo-Random Binary Sequence (PRBS) Generator 5.3.1.6. TX Bit Slip
5.3.1.1. TX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) x
5.3.1.1.1. TX FIFO Low Latency Mode 5.3.1.1.2. TX FIFO Register Mode 5.3.1.1.3. TX FIFO Fast Register Mode
5.3.1.2. Byte Serializer x
5.3.1.2.1. Bonded Byte Serializer 5.3.1.2.2. Byte Serializer Disabled Mode 5.3.1.2.3. Byte Serializer Serialize x2 Mode 5.3.1.2.4. Byte Serializer Serialize x4 Mode
5.3.1.3. 8B/10B Encoder x
5.3.1.3.1. 8B/10B Encoder Control Code Encoding 5.3.1.3.2. 8B/10B Encoder Reset Condition 5.3.1.3.3. 8B/10B Encoder Idle Character Replacement Feature 5.3.1.3.4. 8B/10B Encoder Current Running Disparity Control Feature 5.3.1.3.5. 8B/10B Encoder Bit Reversal Feature 5.3.1.3.6. 8B/10B Encoder Byte Reversal Feature
5.3.2. Receiver Datapath x
5.3.2.1. Word Aligner 5.3.2.2. RX Polarity Inversion Feature 5.3.2.3. Rate Match FIFO 5.3.2.4. 8B/10B Decoder 5.3.2.5. Pseudo-Random Binary Sequence (PRBS) Checker 5.3.2.6. Byte Deserializer 5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS)
5.3.2.1. Word Aligner x
5.3.2.1.1. Word Aligner Bit Slip Mode 5.3.2.1.2. Word Aligner Manual Mode 5.3.2.1.3. Word Aligner Synchronous State Machine Mode 5.3.2.1.4. Word Aligner Deterministic Latency Mode 5.3.2.1.5. Word Aligner Pattern Length for Various Word Aligner Modes 5.3.2.1.6. Word Aligner RX Bit Reversal Feature 5.3.2.1.7. Word Aligner RX Byte Reversal Feature
5.3.2.4. 8B/10B Decoder x
5.3.2.4.1. 8B/10B Decoder Control Code Encoding 5.3.2.4.2. 8B/10B Decoder Running Disparity Checker Feature
5.3.2.6. Byte Deserializer x
5.3.2.6.1. Byte Deserializer Disabled Mode 5.3.2.6.2. Byte Deserializer Deserialize x2 Mode 5.3.2.6.3. Byte Deserializer Deserialize x4 Mode 5.3.2.6.4. Bonded Byte Deserializer
5.3.2.7. RX FIFO (Shared with Enhanced PCS and PCIe* Gen3 PCS) x
5.3.2.7.1. RX FIFO Low Latency Mode 5.3.2.7.2. RX FIFO Register Mode
5.4. Arria 10 PCI Express* Gen3 PCS Architecture x
5.4.1. Transmitter Datapath 5.4.2. Receiver Datapath 5.4.3. PIPE Interface
5.4.1. Transmitter Datapath x
5.4.1.1. TX FIFO (Shared with Standard and Enhanced PCS) 5.4.1.2. Gearbox
5.4.2. Receiver Datapath x
5.4.2.1. Block Synchronizer 5.4.2.2. Rate Match FIFO 5.4.2.3. RX FIFO (Shared with Standard and Enhanced PCS)
5.4.3. PIPE Interface x
5.4.3.1. Auto Speed Negotiation 5.4.3.2. Clock Data Recovery Control
6. Reconfiguration Interface and Dynamic Reconfiguration x
6.1. Reconfiguring Channel and PLL Blocks 6.2. Interacting with the Reconfiguration Interface 6.3. Configuration Files 6.4. Multiple Reconfiguration Profiles 6.5. Embedded Reconfiguration Streamer 6.6. Arbitration 6.7. Recommendations for Dynamic Reconfiguration 6.8. Steps to Perform Dynamic Reconfiguration 6.9. Direct Reconfiguration Flow 6.10. Native PHY IP or PLL IP Core Guided Reconfiguration Flow 6.11. Reconfiguration Flow for Special Cases 6.12. Changing PMA Analog Parameters 6.13. Ports and Parameters 6.14. Dynamic Reconfiguration Interface Merging Across Multiple IP Blocks 6.15. Embedded Debug Features 6.16. Using Data Pattern Generators and Checkers 6.17. Timing Closure Recommendations 6.18. Unsupported Features 6.19. Arria® 10 Transceiver Register Map 6.20. Reconfiguration Interface and Dynamic Revision History
6.2. Interacting with the Reconfiguration Interface x
6.2.1. Reading from the Reconfiguration Interface 6.2.2. Writing to the Reconfiguration Interface
6.11. Reconfiguration Flow for Special Cases x
6.11.1. Switching Transmitter PLL 6.11.2. Switching Reference Clocks
6.11.2. Switching Reference Clocks x
6.11.2.1. ATX Reference Clock Switching 6.11.2.2. fPLL Reference Clock Switching 6.11.2.3. CDR and CMU Reference Clock Switching
6.12. Changing PMA Analog Parameters x
6.12.1. Changing VOD, Pre-emphasis Using Direct Reconfiguration Flow 6.12.2. Changing CTLE Settings in Manual Mode Using Direct Reconfiguration Flow 6.12.3. CTLE Settings in Triggered Adaptation Mode 6.12.4. Enabling and Disabling Loopback Modes Using Direct Reconfiguration Flow
6.15. Embedded Debug Features x
6.15.1. Native PHY Debug Master Endpoint 6.15.2. Optional Reconfiguration Logic
6.15.2. Optional Reconfiguration Logic x
6.15.2.1. Capability Registers 6.15.2.2. Control and Status Registers 6.15.2.3. PRBS Soft Accumulators
6.16. Using Data Pattern Generators and Checkers x
6.16.1. Using PRBS Data Pattern Generator and Checker 6.16.2. Using Pseudo Random Pattern Mode
6.16.1. Using PRBS Data Pattern Generator and Checker x
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs 6.16.1.2. Enabling the PRBS Data Generator in bonded designs 6.16.1.3. Enabling the PRBS Data Checker in non bonded design 6.16.1.4. Enabling the PRBS Checker in bonded designs 6.16.1.5. Disabling/Enabling PRBS Pattern Inversion
6.16.1.1. Enabling the PRBS Data Generator in non bonded designs x
6.16.1.1.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in non bonded designs
6.16.1.2. Enabling the PRBS Data Generator in bonded designs x
6.16.1.2.1. Examples of Enabling the PRBS9 and PRBS31 Pattern Generators in bonded designs
6.16.1.3. Enabling the PRBS Data Checker in non bonded design x
6.16.1.3.1. Examples of Enabling the PRBS Data Checker
6.16.2. Using Pseudo Random Pattern Mode x
6.16.2.1. Enabling Pseudo Random Pattern Mode
7. Calibration x
7.1. Reconfiguration Interface and Arbitration with PreSICE Calibration Engine 7.2. Calibration Registers 7.3. Power-up Calibration 7.4. User Recalibration 7.5. Calibration Example 7.6. Calibration Revision History
7.2. Calibration Registers x
7.2.1. Avalon® Memory-Mapped Interface Arbitration Registers 7.2.2. Transceiver Channel Calibration Registers 7.2.3. Fractional PLL Calibration Registers 7.2.4. ATX PLL Calibration Registers 7.2.5. Capability Registers 7.2.6. Rate Switch Flag Register
7.4. User Recalibration x
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data Rate Change
7.4.1. Recalibration After Transceiver Reference Clock Frequency or Data Rate Change x
7.4.1.1. User Recalibration
7.5. Calibration Example x
7.5.1. ATX PLL Recalibration 7.5.2. Fractional PLL Recalibration 7.5.3. CDR/CMU PLL Recalibration 7.5.4. PMA Recalibration
8. Analog Parameter Settings x
8.1. Making Analog Parameter Settings using the Assignment Editor 8.2. Updating Quartus Settings File with the Known Assignment 8.3. Analog Parameter Settings List 8.4. Receiver General Analog Settings 8.5. Receiver Analog Equalization Settings 8.6. Transmitter General Analog Settings 8.7. Transmitter Pre-Emphasis Analog Settings 8.8. Transmitter VOD Settings 8.9. Dedicated Reference Clock Settings 8.10. Unused Transceiver RX Channels Settings 8.11. Analog Parameter Settings Revision History
8.4. Receiver General Analog Settings x
8.4.1. XCVR_A10_RX_LINK 8.4.2. XCVR_A10_RX_TERM_SEL 8.4.3. XCVR_VCCR_VCCT_VOLTAGE - RX
8.5. Receiver Analog Equalization Settings x
8.5.1. CTLE Settings 8.5.2. VGA Settings 8.5.3. Decision Feedback Equalizer (DFE) Settings
8.5.1. CTLE Settings x
8.5.1.1. XCVR_A10_RX_ONE_STAGE_ENABLE 8.5.1.2. XCVR_A10_RX_EQ_DC_GAIN_TRIM 8.5.1.3. XCVR_A10_RX_ADP_CTLE_ACGAIN_4S 8.5.1.4. XCVR_A10_RX_ADP_CTLE_EQZ_1S_SEL
8.5.2. VGA Settings x
8.5.2.1. XCVR_A10_RX_ADP_VGA_SEL
8.5.3. Decision Feedback Equalizer (DFE) Settings x
8.5.3.1. XCVR_A10_RX_ADP_DFE_FXTAP
8.6. Transmitter General Analog Settings x
8.6.1. XCVR_A10_TX_LINK 8.6.2. XCVR_A10_TX_TERM_SEL 8.6.3. XCVR_A10_TX_COMPENSATION_EN 8.6.4. XCVR_VCCR_VCCT_VOLTAGE - TX 8.6.5. XCVR_A10_TX_SLEW_RATE_CTRL
8.7. Transmitter Pre-Emphasis Analog Settings x
8.7.1. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_1T 8.7.2. XCVR_A10_TX_PRE_EMP_SIGN_PRE_TAP_2T 8.7.3. XCVR_A10_TX_PRE_EMP_SIGN_1ST_POST_TAP 8.7.4. XCVR_A10_TX_PRE_EMP_SIGN_2ND_POST_TAP 8.7.5. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T 8.7.6. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T 8.7.7. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP 8.7.8. XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP
8.8. Transmitter VOD Settings x
8.8.1. XCVR_A10_TX_VOD_OUTPUT_SWING_CTRL
8.9. Dedicated Reference Clock Settings x
8.9.1. XCVR_A10_REFCLK_TERM_TRISTATE 8.9.2. XCVR_A10_TX_XTX_PATH_ANALOG_MODE
9. Debugging Transceiver Toolkit x
9.1. Transceiver Toolkit GUI 9.2. Transceiver Debugging Flow Walkthrough 9.3. Linking Hardware Resource for Multiple FPGAs 9.4. Troubleshooting Common Errors 9.5. Debugging Transceiver Toolkit Revision History
9.1. Transceiver Toolkit GUI x
9.1.1. Main View Functions
9.2. Transceiver Debugging Flow Walkthrough x
9.2.1. Enabling Transceiver Toolkit Support 9.2.2. Programming Design into an Intel® FPGA 9.2.3. Loading Design to the Transceiver Toolkit 9.2.4. Creating Transceiver Links 9.2.5. Running Link Test
9.2.4. Creating Transceiver Links x
9.2.4.1. Transceiver Toolkit Parameter Settings 9.2.4.2. Verifying Hardware Connections
9.2.5. Running Link Test x
9.2.5.1. Running BER Tests 9.2.5.2. Link Optimization Tests
9.3. Linking Hardware Resource for Multiple FPGAs x
9.3.1. Linking One Design to One Device 9.3.2. Linking Two Designs to Two Devices 9.3.3. Linking One Design on Two Devices 9.3.4. Linking Designs and Devices on Separate Boards
1. Arria® 10 Transceiver PHY Overview
2. Implementing Protocols in Arria 10 Transceivers
3. PLLs and Clock Networks
4. Resetting Transceiver Channels
5. Arria 10 Transceiver PHY Architecture
6. Reconfiguration Interface and Dynamic Reconfiguration
7. Calibration
8. Analog Parameter Settings
9. Debugging Transceiver Toolkit

2.4.7. Dynamic Reconfiguration Parameters

Dynamic reconfiguration allows you to change the behavior of the transceiver channels and PLLs without powering down the device.

Each transceiver channel and PLL includes an Avalon® memory-mapped interface slave interface for reconfiguration. This interface provides direct access to the programmable address space of each channel and PLL. Because each channel and PLL includes a dedicated Avalon® memory-mapped interface slave interface, you can dynamically modify channels either concurrently or sequentially. If your system does not require concurrent reconfiguration, you can parameterize the Transceiver Native PHY IP to share a single reconfiguration interface.

You can use dynamic reconfiguration to change many functions and features of the transceiver channels and PLLs. For example, you can change the reference clock input to the TX PLL. You can also change between the Standard and Enhanced datapaths.

To enable Arria® 10 transceiver toolkit capability in the Native PHY IP core, you must enable the following options:

  • Enable dynamic reconfiguration
  • Enable Native PHY Debug Master Endpoint
  • Enable capability registers
  • Enable control and status registers
  • Enable PRBS (Pseudo Random Binary Sequence) soft accumulators
Table 38.  Dynamic Reconfiguration
Parameter Value Description
Enable dynamic reconfiguration On/Off When you turn on this option, the dynamic reconfiguration interface is enabled.
Share reconfiguration interface On/Off When you turn on this option, the Transceiver Native PHY IP presents a single Avalon® memory-mapped interface slave interface for dynamic reconfiguration for all channels. In this configuration, the upper [n-1:10] address bits of the reconfiguration address bus specify the channel. The channel numbers are binary encoded. Address bits [9:0] provide the register offset address within the reconfiguration space for a channel.
Enable Native PHY Debug Master Endpoint On/Off When you turn on this option, the Transceiver Native PHY IP includes an embedded Native PHY Debug Master Endpoint (NPDME) that connects internally to the Avalon® memory-mapped interface slave interface for dynamic reconfiguration. The NPDME can access the reconfiguration space of the transceiver. It can perform certain test and debug functions via JTAG using the System Console. This option requires you to enable the Share reconfiguration interface option for configurations using more than one channel.
Separate reconfig_waitrequest from the status of AVMM arbitration with PreSICE On/Off When enabled, the reconfig_waitrequest does not indicate the status of Avalon® memory-mapped interface arbitration with PreSICE. The Avalon® memory-mapped interface arbitration status is reflected in a soft status register bit. This feature requires that the "Enable control and status registers" feature under "Optional Reconfiguration Logic" be enabled.
Table 39.  Optional Reconfiguration Logic
Parameter Value Description
Enable capability registers On/Off Enables capability registers that provide high level information about the configuration of the transceiver channel.
Set user-defined IP identifier User-defined Sets a user-defined numeric identifier that can be read from the user_identifier offset when the capability registers are enabled.
Enable control and status registers On/Off Enables soft registers to read status signals and write control signals on the PHY interface through the embedded debug.
Enable PRBS (Pseudo Random Binary Sequence) soft accumulators On/Off Enables soft logic for performing PRBS bit and error accumulation when the hard PRBS generator and checker are used.
Table 40.  Configuration Files
Parameter Value Description
Configuration file prefix <prefix> Here, the file prefix to use for generated configuration files is specified. Each variant of the Transceiver Native PHY IP should use a unique prefix for configuration files.
Generate SystemVerilog package file On/Off When you turn on this option, the Transceiver Native PHY IP generates a SystemVerilog package file, reconfig_parameters.sv. This file contains parameters defined with the attribute values required for reconfiguration.
Generate C header file On/Off When you turn on this option, the Transceiver Native PHY IP generates a C header file, reconfig_parameters.h. This file contains macros defined with the attribute values required for reconfiguration.
Generate MIF (Memory Initialization File) On/Off When you turn on this option, the Transceiver Native PHY IP generates a MIF, reconfig_parameters.mif. This file contains the attribute values required for reconfiguration in a data format.
Include PMA analog settings in configuration files On/Off When enabled, the IP allows you to configure the PMA analog settings that are selected in the Analog PMA settings (Optional) tab. These settings are included in your generated configuration files.
Note: You must still specify the analog settings for your current configuration using Quartus Prime Setting File (.qsf) assignments in Quartus. This option does not remove the requirement to specify Quartus Prime Setting File (.qsf) assignments for your analog settings. Refer to the Analog Parameter Settings chapter in the Arria® 10 Transceiver PHY User Guide for details on using the QSF assignments.
Table 41.  Configuration Profiles
Parameter Value Description
Enable multiple reconfiguration profiles On/Off When enabled, you can use the GUI to store multiple configurations. This information is used by Quartus to include the necessary timing arcs for all configurations during timing driven compilation. The Native PHY generates reconfiguration files for all of the stored profiles. The Native PHY also checks your multiple reconfiguration profiles for consistency to ensure you can reconfigure between them. Among other things this checks that you have exposed the same ports for each configuration.28
Enable embedded reconfiguration streamer On/Off Enables the embedded reconfiguration streamer, which automates the dynamic reconfiguration process between multiple predefined configuration profiles. This is optional and increases logic utilization. The PHY includes all of the logic and data necessary to dynamically reconfigure between pre-configured profiles.
Generate reduced reconfiguration files On/Off When enabled, The Native PHY generates reconfiguration report files containing only the attributes or RAM data that are different between the multiple configured profiles. The reconfiguration time decreases with the use of reduced .mif files.
Number of reconfiguration profiles 1-8 Specifies the number of reconfiguration profiles to support when multiple reconfiguration profiles are enabled.
Selected reconfiguration profile 0-7 Selects which reconfiguration profile to store/load/clear/refresh, when clicking the relevant button for the selected profile.
Store configuration to selected profile - Clicking this button saves or stores the current Native PHY parameter settings to the profile specified by the Selected reconfiguration profile parameter.
Load configuration from selected profile - Clicking this button loads the current Native PHY with parameter settings from the stored profile specified by the Selected reconfiguration profile parameter.
Clear selected profile - Clicking this button clears or erases the stored Native PHY parameter settings for the profile specified by the Selected reconfiguration profile parameter. An empty profile defaults to the current parameter settings of the Native PHY.
Clear all profiles - Clicking this button clears the Native PHY parameter settings for all the profiles.
Refresh selected profile - Clicking this button is equivalent to clicking the Load configuration from selected profile and Store configuration to selected profile buttons in sequence. This operation loads the Native PHY parameter settings from stored profile specified by the Selected reconfiguration profile parameter and subsequently stores or saves the parameters back to the profile.
Table 42.  Analog PMA Settings (Optional) for Dynamic Reconfiguration
Parameter Value Description
TX Analog PMA Settings
Analog Mode (Load Intel-recommended Default settings) Cei_11100_lr to xfp_9950 Selects the analog protocol mode to pre-select the TX pin swing settings (VOD, Pre-emphasis, and Slew Rate). After loading the pre-selected values in the GUI, if one or more of the individual TX pin swing settings need to be changed, then enable the option to override the Intel-recommended defaults to individually modify the settings.
Override Intel-recommended Analog Mode Default settings On/Off Enables the option to override the Intel-recommended settings for the selected TX Analog Mode for one or more TX analog parameters.
Output Swing Level (VOD) 0-31 Selects the transmitter programmable output differential voltage swing.
Pre-Emphasis First Pre-Tap Polarity

Fir_pre_1t_neg

Fir_pre_1t_pos

Selects the polarity of the first pre-tap for pre-emphasis.
Pre-Emphasis First Pre-Tap Magnitude 0-16 29 Selects the magnitude of the first pre-tap for pre-emphasis
Pre-Emphasis Second Pre-Tap Polarity

Fir_pre_2t_neg

Fir_pre_2t_pos

Selects the polarity of the second pre-tap for pre-emphasis.
Pre-Emphasis Second Pre-Tap Magnitude 0-7 30 Selects the magnitude of the second pre-tap for pre-emphasis.
Pre-Emphasis First Post-Tap Polarity

Fir_post_1t_neg

Fir_post_1t_pos

 Selects the polarity of the first post-tap for pre-emphasis
Pre-Emphasis First Post-Tap Magnitude 0-25 31 Selects the magnitude of the first post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Polarity

Fir_post_2t_neg

Fir_post_2t_pos

Selects the polarity of the second post-tap for pre-emphasis.
Pre-Emphasis Second Post-Tap Magnitude 0-12 32 Selects the magnitude of the second post-tap for pre-emphasis
Slew Rate Control slew_r0 to slew_r5 Selects the slew rate of the TX output signal. Valid values span from slowest to the fastest rate.
High-Speed Compensation Enable/Disable Enables the power-distribution network (PDN) induced inter-symbol interference (ISI) compensation in the TX driver. When enabled, it reduces the PDN induced ISI jitter, but increases the power consumption.
On-Chip termination

r_r1

r_r2

Selects the on-chip TX differential termination.
RX Analog PMA settings
Override Intel-recommended Default settings On/Off Enables the option to override the Intel-recommended settings for one or more RX analog parameters
CTLE (Continuous Time Linear Equalizer) mode

non_s1_mode

S1_mode

Selects between the RX high gain mode non_s1_mode or RX high data rate mode s1_mode for the Continuous Time Linear Equalizer (CTLE).
DC gain control of high gain mode CTLE No_dc_gain to stg4_gain7 Selects the DC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode
AC Gain Control of High Gain Mode CTLE radp_ctle_acgain_4s_0 to radp_ctle_acgain_4s_28 Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high gain mode when CTLE is in manual mode.
AC Gain Control of High Data Rate Mode CTLE radp_ctle_eqz_1s_sel_0 to Radp_ctle_eqz_1s_sel_15 Selects the AC gain of the Continuous Time Linear Equalizer (CTLE) in high data rate mode when CTLE is in manual mode.
Variable Gain Amplifier (VGA) Voltage Swing Select radp_vga_sel_0 to radp_vga_sel_7 Selects the Variable Gain Amplifier (VGA) output voltage swing when both the CTLE and DFE blocks are in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 1 Co-efficient radp_dfe_fxtap1_0 to radp_dfe_fxtap1_127 Selects the co-efficient of the fixed tap 1 of the Decision Feedback Equalizer (DFE) when operating in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 2 Co-efficient radp_dfe_fxtap2_0 to radp_dfe_fxtap2_127 Selects the co-efficient of the fixed tap 2 of the Decision Feedback Equalizer (DFE) when operating in manual mode
Decision Feedback Equalizer (DFE) Fixed Tap 3 Co-efficient radp_dfe_fxtap3_0 to radp_dfe_fxtap3_127 Selects the co-efficient of the fixed tap 3 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 4 Co-efficient radp_dfe_fxtap4_0 to radp_dfe_fxtap4_63

Selects the co-efficient of the fixed tap 4 of the Decision Feedback Equalizer (DFE) when operating in manual mode.

Decision Feedback Equalizer (DFE) Fixed Tap 5 Co-efficient radp_dfe_fxtap5_0 to radp_dfe_fxtap5_63

Selects the co-efficient of the fixed tap 5 of the Decision Feedback Equalizer (DFE) when operating in manual mode.

Decision Feedback Equalizer (DFE) Fixed Tap 6 Co-efficient radp_dfe_fxtap6_0 to radp_dfe_fxtap6_31 Selects the co-efficient of the fixed tap 6 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 7 Co-efficient radp_dfe_fxtap7_0 to radp_dfe_fxtap7_31 Selects the co-efficient of the fixed tap 7 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 8 Co-efficient radp_dfe_fxtap8_0 to radp_dfe_fxtap8_31

Selects the co-efficient of the fixed tap 8 of the Decision Feedback Equalizer (DFE) when operating in manual mode.

Decision Feedback Equalizer (DFE) Fixed Tap 9 Co-efficient radp_dfe_fxtap9_0 to radp_dfe_fxtap9_31 Selects the co-efficient of the fixed tap 9 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 10 Co-efficient radp_dfe_fxtap10_0 to radp_dfe_fxtap10_31 Selects the co-efficient of the fixed tap 10 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
Decision Feedback Equalizer (DFE) Fixed Tap 11 Co-efficient radp_dfe_fxtap11_0 to radp_dfe_fxtap11_31 Selects the co-efficient of the fixed tap 11 of the Decision Feedback Equalizer (DFE) when operating in manual mode.
On-Chip termination R_ext0, r_r1, r_r2 Selects the on-chip RX differential termination.
Table 43.  Generation Options
Parameter Value Description
Generate parameter documentation file On/Off When you turn on this option, generation produces a Comma-Separated Value (.csv ) file with descriptions of the Transceiver Native PHY IP parameters.
Related Information
28 For more information on timing closure, refer to the Reconfiguration Interface and Dynamic Reconfiguration chapter.
29 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_1T section of the Analog Parameter Settings chapter.
30 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_PRE_TAP_2T section of the Analog Parameter Settings chapter.
31 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_1ST_POST_TAP section of the Analog Parameter Settings chapter.
32 For more information refer to Available Options table in the XCVR_A10_TX_PRE_EMP_SWITCHING_CTRL_2ND_POST_TAP section of the Analog Parameter Settings chapter.
Level Two Title