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1.1. Directory Structure
1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements
1.3. Generating the DisplayPort Intel® FPGA IP Design Example
1.4. Simulating the Design
1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design
1.6. DisplayPort Intel® FPGA IP Design Example Parameters
2.1. Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features
2.2. Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features
2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features
2.4. Enabling Adaptive Sync Support
2.5. Design Components
2.6. Clocking Scheme
2.7. Interface Signals and Parameter
2.8. Hardware Setup
2.9. Simulation Testbench
2.10. DisplayPort Transceiver Reconfiguration Flow
2.11. Transceiver Lane Configurations
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1.5.1. Regenerating .elf File
By default, the IP regenerates the .elf file when you generate the dynamic design example. However, in some cases, you need to regenerate the .elf file if you modify the software file or regenerate the dp_core.qsys file. Regenerating the dp_core.qsys file updates the .sopcinfo file, which requires you to regenerate the ELF file.
- Go to <project directory>/niosv_software and edit the code if necessary.
- Go to <project directory>/script and execute the following build script:
- On Windows:
- Search and open Nios® V Command Shell.
- In the Nios® V Command Shell, go to <project directory>\script and execute quartus_py .\build_niosv_sw.py -d.
- On Linux:
- Launch a Nios® V Shell, $QUARTUS_ROOTDIR/../niosv/bin/niosv-shell.
- In the Nios® V Shell, go to <project directory>/script and execute quartus_py ./build_niosv_sw.py -d.
- On Windows:
- Make sure an .elf file is generated in <project directory>/software/dp_demo.
- Download the generated .elf file into the FPGA without recompiling the .sof file by running the following script:
niosv-download <project directory>/software/dp_demo/*.elf
- Push the reset button on the FPGA board for the new software to take effect.