DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

Download PDF
ID 683603
Date 4/29/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. DisplayPort Intel® FPGA IP Design Example Hardware and Software Requirements 1.3. Generating the DisplayPort Intel® FPGA IP Design Example 1.4. Simulating the Design 1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the DisplayPort Intel® FPGA IP Design x
1.5.1. Regenerating .elf File
2. Parallel Loopback Design Examples x
2.1. Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features 2.4. Enabling Adaptive Sync Support 2.5. Design Components 2.6. Clocking Scheme 2.7. Interface Signals and Parameter 2.8. Hardware Setup 2.9. Simulation Testbench 2.10. DisplayPort Transceiver Reconfiguration Flow 2.11. Transceiver Lane Configurations
2.3. Cyclone® 10 GX DisplayPort SST TX-only or RX-only Design Features x
2.3.1. Cyclone® 10 GX DisplayPort SST TX-only Design Features 2.3.2. Cyclone® 10 GX DisplayPort SST RX-only Design Features
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Cyclone® 10 GX FPGA IP Design Example User Guide

1.6. DisplayPort Intel® FPGA IP Design Example Parameters

Table 6.   DisplayPort Intel® FPGA IP Design Example Parameters for Cyclone® 10 GX Devices
Parameter Value Description
Available Design Example
Select Design
  • None
  • DisplayPort SST TX-only
  • DisplayPort SST RX-only
  • DisplayPort SST Parallel Loopback with PCR
  • DisplayPort SST Parallel Loopback without PCR
  • DisplayPort MST Parallel Loopback with PCR
  • DisplayPort MST Parallel Loopback without PCR
 Select the design example to be generated.
  • None: No design example is available for the current parameter selection
  • DisplayPort SST RX-only: This design example demonstrates serial loopback of DisplayPort sink when you turn off the Enable Video Input Image Port parameter.
  • DisplayPort SST TX-only: This design example demonstrates serial loopback of DisplayPort source when you turn off both RX SUPPORT DP and Enable Video Input Image Port parameters.
  • DisplayPort SST RX-only: This design example demonstrates serial loopback of DisplayPort sink when you turn off the TX SUPPORT DP parameter.
  • DisplayPort SST Parallel Loopback with PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source through a Pixel Clock Recovery (PCR) module when you turn off the Enable Video Input Image Port parameter.
  • DisplayPort SST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
  • DisplayPort MST Parallel Loopback with PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source through a Pixel Clock Recovery (PCR) module when you turn off the Enable Video Input Image Port parameter and turn on the Support MST parameter for TX and RX.
  • DisplayPort MST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter and turn on the Support MST parameter for TX and RX.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Synthesis On, Off Turn on this option to generate the necessary files for Quartus® Prime compilation and hardware demonstration.
Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Target Development Kit
Select Board
  • No Development Kit
  • Cyclone® 10 GX FPGA Development Kit
  • Custom Development Kit
 Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Cyclone® 10 GX FPGA Development Kit: This option automatically selects the project's target device to match the device on this development kit. You may change the target device using the Change Target Device parameter if your board revision has a different device variant. The IP core sets all pin assignments according to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA. You may need to set the pin assignments on your own.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
Level Two Title