DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

ID 683603
Date 9/28/2020
Public

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2.10. Transceiver Lane Configurations

If you want to configure your design to use 1, 2 or 4 lanes targeting different versions of Bitec FMC daughter cards, you have to configure the pin assignments accordingly in the Intel® Quartus® Prime Pro Settings File (QSF).
To configure the DisplayPort Intel® FPGA IP design example using 1, 2 or 4 lanes, follow these steps:
  1. In both the DisplayPort Source and Sink parameter editors, set the Maximum lane count parameter to 1, 2 or 4.
  2. Generate the design example.
  3. Make the following assignments in the Assignment Editor.
    Table 24.  Pin Assignments for Bitec FMC Revision 8 or Earlier
    DisplayPort Pin Location

    ( Intel® Cyclone® 10 GX Development Kit)

    Four Lanes Two Lanes One Lane
    Source AG28 fmca_dp_c2m_p[0] Not applicable Not applicable
    AG27 fmca_dp_c2m_n[0]
    AE28 fmca_dp_c2m_p[1]
    AE27 fmca_dp_c2m_n[1]
    AC28 fmca_dp_c2m_p[2] fmca_dp_c2m_p[0]
    AC27 fmca_dp_c2m_n[2] fmca_dp_c2m_n[0]
    AA28 fmca_dp_c2m_p[3] fmca_dp_c2m_p[1] fmca_dp_c2m_p[0]
    AA27 fmca_dp_c2m_n[3] fmca_dp_c2m_n[1] fmca_dp_c2m_n[0]
    Sink AF26 fmca_dp_m2c_p[0] fmca_dp_m2c_p[0] fmca_dp_m2c_p[0]
    AF25 fmca_dp_m2c_n[0] fmca_dp_m2c_n[0] fmca_dp_m2c_n[0]
    AD26 fmca_dp_m2c_p[1] fmca_dp_m2c_p[1] Not applicable
    AD25 fmca_dp_m2c_n[1] fmca_dp_m2c_n[1]
    AB26 fmca_dp_m2c_p[2] Not applicable
    AB25 fmca_dp_m2c_n[2]
    Y26 fmca_dp_m2c_p[3]
    Y25 fmca_dp_m2c_n[3]
    Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable
    Table 25.  Pin Assignments for Bitec FMC Revision 10
    DisplayPort Pin Location ( Intel® Cyclone® 10 GX Development Kit) Four Lanes Two Lanes One lane
    Source AG28 fmc_dp_c2m_p[0] fmc_dp_c2m_p[0] fmc_dp_c2m_p[0]
    AG27 fmc_dp_c2m_n[0] fmc_dp_c2m_n[0] fmc_dp_c2m_n[0]
    AE28 fmc_dp_c2m_p[1] fmc_dp_c2m_p[1] Not Applicable
    AE27 fmc_dp_c2m_n[1] fmc_dp_c2m_n[1]
    AC28 fmc_dp_c2m_p[2] Not Applicable
    AC27 fmc_dp_c2m_n[2]
    AA28 fmc_dp_c2m_p[3]
    AA27 fmc_dp_c2m_n[3]
    Sink AF26 fmc_dp_m2c_p[0] fmc_dp_m2c_p[0] fmc_dp_m2c_p[0]
    AF25 fmc_dp_m2c_n[0] fmc_dp_m2c_n[0] fmc_dp_m2c_n[0]
    AD26 fmc_dp_m2c_p[1] fmc_dp_m2c_p[1] Not Applicable
    AD25 fmc_dp_m2c_n[1] fmc_dp_m2c_n[1]
    AB26 fmc_dp_m2c_p[2] Not Applicable
    AB25 fmc_dp_m2c_n[2]
    Y26 fmc_dp_m2c_p[3]
    Y25 fmc_dp_m2c_n[3]
    Merging of Reconfiguration Interfaces XCVR_RECONFIG_GROUP Enable Enable Enable
    Table 26.  Pin Assignments for Bitec FMC Revision 11
    DisplayPort Pin Location

    ( Intel® Cyclone® 10 GX Development Kit)

    Four Lanes Two Lanes One Lane
    Source AG28 fmca_dp_c2m_p[0] fmca_dp_c2m_p[0] fmca_dp_c2m_p[0]
    AG27 fmca_dp_c2m_n[0] fmca_dp_c2m_n[0] fmca_dp_c2m_n[0]
    AE28 fmca_dp_c2m_p[1] fmca_dp_c2m_p[1] Not applicable
    AE27 fmca_dp_c2m_n[1] fmca_dp_c2m_n[1]
    AC28 fmca_dp_c2m_p[2] Not applicable
    AC27 fmca_dp_c2m_n[2]
    AA28 fmca_dp_c2m_p[3]
    AA27 fmca_dp_c2m_n[3]
    Sink AF26 fmca_dp_m2c_p[0] Not applicable Not applicable
    AF25 fmca_dp_m2c_n[0]
    AD26 fmca_dp_m2c_p[1]
    AD25 fmca_dp_m2c_n[1]
    AB26 fmca_dp_m2c_p[2] fmca_dp_m2c_p[0]
    AB25 fmca_dp_m2c_n[2] fmca_dp_m2c_n[0]
    Y26 fmca_dp_m2c_p[3] fmca_dp_m2c_p[1] fmca_dp_m2c_p[0]
    Y25 fmca_dp_m2c_n[3] fmca_dp_m2c_n[1] fmca_dp_m2c_n[0]
    Transceiver Avalon® Memory-Mapped Interface Group XCVR_RECONFIG_GROUP Enable Disable Disable
    Note: You can disable the non-applicable pin assignments in the Assignment Editor.