DisplayPort Intel® Cyclone 10 GX FPGA IP Design Example User Guide

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ID 683603
Date 9/28/2020
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Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. Parallel Loopback Design Examples 3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives 4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. Parallel Loopback Design Examples x
2.1. Intel® Cyclone® 10 GX DisplayPort SST Parallel Loopback Design Features 2.2. Intel® Cyclone® 10 GX DisplayPort MST Parallel Loopback Design Features 2.3. Enabling Adaptive Sync Support 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameter 2.7. Hardware Setup 2.8. Simulation Testbench 2.9. DisplayPort Transceiver Reconfiguration Flow 2.10. Transceiver Lane Configurations
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. Parallel Loopback Design Examples
3. DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide Archives
4. Revision History for DisplayPort Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

1.1. Directory Structure

The directories contain the generated files for the DisplayPort design example.
Figure 2. Directory Structure for the Design Example
Table 1.  Other Generated Files in RTL Folder
Folders Files
clkrec /altera_pll_reconfig_core.v
/altera_pll_reconfig_mif_reader.v
/altera_pll_reconfig_top.v
/bitec_clkrec.qip
/bitec_clkrec.sdc
/bitec_clkrec.v
/bitec_dp_add.v
/bitec_dp_cdc.v
/bitec_dp_cdc_fifo.v
/bitec_dp_cdc_pulse.v
/bitec_dp_cnt.v
/bitec_dp_dcfifo.v
/bitec_dp_dd.v
/bitec_dp_div.v
/bitec_dp_mult.v
/bitec_fpll_calc.v
/bitec_fpll_cntrl.v
/bitec_fpll_reconf.v
/bitec_loop_cntrl.v
/bitec_vsyngen.v
/clkrec_pll135_c10.ip
/clkrec_pll1_c10.ip
/clkrec_reset_c10.ip
<Platform Designer generated folder>
core /dp_core.ip
/dp_rx.ip
/dp_tx.ip
<Platform Designer generated folder>
rx_phy /gxb_rx.ip
/gxb_rx_reset.ip
/rx_phy_top.v
<Platform Designer generated folder>
tx_phy /gxb_tx.ip
/gxb_tx_reset.ip
/gxb_tx_fpll.ip
/tx_phy_top.v
<Platform Designer generated folder>
Table 2.   Other Generated Files in Simulation Folder
Folders Files
aldec /aldec.do
/rivierapro_setup.tcl
cadence /cds.lib
/hdl.var
/ncsim.sh
/ncsim_setup.sh
<cds_libs folder>
core /dp_core.ip
/dp_rx.ip
/dp_tx.ip
<Platform Designer generated folder>
mentor /mentor.do
/msim_setup.tcl
xcelium /cds.lib
/hdl.var
/xcelium_sim.sh
/xcelium_setup.sh
<cds_libs folder>
rx_phy /gxb_rx.ip
/rx_phy_top.v
/gxb_rx_reset.ip
<Platform Designer generated folder>
synopsys /vcs/filelist.f
/vcs/vcs_setup.sh
/vcs/vcs_sim.sh
/vcsmx/synopsys_sim_setup
/vcsmx/vcsmx_setup.sh
/vcsmx/vcsmx_sim.sh
testbench /c10_dp_harness.sv
/clk_gen.v
/freq_check.v
/rx_freq_check.v
/tx_freq_check.v
/vga_driver.v
tx_phy /gxb_tx.ip
/gxb_tx_reset.ip
<Platform Designer generated folder>
/gxb_tx_fpll.ip
/tx_phy_top.v
Level Two Title