CPRI Intel® FPGA IP User Guide

ID 683595
Date 11/15/2022
Public

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Document Table of Contents

3.19.1. CPRI Link

The CPRI Intel® FPGA IP configures the interface to the CPRI serial link in an Intel® FPGA device transceiver channel.
Table 42.  CPRI Link Interface Signals

Signal Name

Direction

Description

xcvr_rxdatain

Input

High-speed serial data receiver port.
xcvr_txdataout

Output

High-speed serial data transmitter port.
xcvr_los

Input

Asynchronous signal that forces link to LOS state for quick resynchronization.

If you implement the CPRI link with a fiber optic channel, you could connect this input signal to the SFP module LOS signal so that it is asserted when the SFP module loses signal. Otherwise, you should tie this signal to the value of 0.