Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

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Date 12/01/2017
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Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition) x
Step 1: Open the Project and Compile Step 2: Specify Clock Constraints Step 3: View Clock Timing Analysis Step 4: Declare False Paths Step 5: View Post-Fit Timing Results Step 6: Specify Input and Output Delay Constraints Step 7: Report Clocks and Top Failing Paths Document Revision History
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)

Step 6: Specify Input and Output Delay Constraints

Accurate timing analysis requires constraining all input and output ports. Follow these steps to identify unconstrained paths and apply input and output delay constraints to the ports.
  1. To identify unconstrained path in the design, double-click Report Unconstrained Paths the Diagnostic reports. The report lists the details of all unconstrained paths.
  2. Repeat the steps in Step 2: Specify Clock Constraints to open the .sdc file for edit.
  3. In the .sdc file, locate the following section: 
    #**************************************************************
# Set Input Delay
#**************************************************************
  4. To insert the set_input_delay constraint, right-click under the # Set Input Delay comment, and then click Insert Constraint > Set Input Delay.
  5. In the Set Input Delay dialog box, specify the following options for the constraint:
    Option Setting
    Clock name clk
    Use falling clock edge Off
    Delay value 2
    Targets
    • Collection—get_ports
    • Filter—d* newt reset
    • SDC Command 
      [get_ports {d[0] d[1] d[2] d[3] d[4] /
     d[5] d[6] d[7] newt reset}]
  6. Click Insert. The following constraint appears at the insertion point: 
    set_input_delay -clock { clk } 2 [get_ports /
     {d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] newt reset}]
  7. Repeat steps 4 through 6 to add the following set_output_delay constraint in the # Set Output Delay section of the .sdc file:
    Option Setting
    Clock name clk
    Use falling clock edge Off
    Delay value 1.5
    Targets
    • Collection—get_ports
    • Filter—d* newt reset
    • SDC Command 
      [get_ports {follow yn_out[0] yn_out[1] yn_out[2] /
     yn_out[3] yn_out[4] yn_out[5] yn_out[6] /
     yn_out[7] yvalid}]
  8. Click Insert. The following constraint appears at the insertion point. All input and output ports now have constraints: 
    set_output_delay -clock { clk } 1.5 [get_ports /
     {follow yn_out[0] yn_out[1] yn_out[2] yn_out[3] yn_out[4] /
     yn_out[5] yn_out[6] yn_out[7] yvalid}]
  9. Save and close the .sdc file.
  10. Double-click Read SDC File, and then double-click Update Timing Netlist in the Tasks pane. You can now verify there are no remaining unconstrained paths.
  11. Double-click Report Unconstrained Paths in the Diagnostic reports. The report shows zero unconstrained paths.
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