Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

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Date 12/01/2017
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Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition) x
Step 1: Open the Project and Compile Step 2: Specify Clock Constraints Step 3: View Clock Timing Analysis Step 4: Declare False Paths Step 5: View Post-Fit Timing Results Step 6: Specify Input and Output Delay Constraints Step 7: Report Clocks and Top Failing Paths Document Revision History
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)

Step 3: View Clock Timing Analysis

Follow these steps to confirm the clock constraints and view timing analysis results.
  1. In the Tasks pane, double-click Report SDC in the Diagnostic reports. The Create Clock report shows your new clock constraints.
  2. To generate clock timing performance summary report, double-click Report Clocks on the Tasks pane.
  3. To verify the validity of all clock-to-clock transfers, double-click Report Clock Transfers on the Tasks pane.

    The Setup Transfers report indicates that a clock-to-clock transfer exists between clk and clkx2. The RR Paths column lists the number of instances where clk clocks the source node, and clkx2 clocks the destination node. These clock transfers actually do not require analysis because they are false paths in the design. The next step demonstrates declaring these false paths.

Level Two Title