Timing Analyzer Quick-Start Tutorial: Intel® Quartus® Prime Pro Edition

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ID 683588
Date 12/01/2017
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Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition) x
Step 1: Open the Project and Compile Step 2: Specify Clock Constraints Step 3: View Clock Timing Analysis Step 4: Declare False Paths Step 5: View Post-Fit Timing Results Step 6: Specify Input and Output Delay Constraints Step 7: Report Clocks and Top Failing Paths Document Revision History
Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)

Timing Analyzer Quick-Start Tutorial ( Intel® Quartus® Prime Pro Edition)

Updated for:
Intel® Quartus® Prime Design Suite 17.1
This tutorial demonstrates how to specify timing constraints and perform static timing analysis with the Intel® Quartus® Prime Timing Analyzer. The Timing Analyzer validates the timing performance of all logic in your design using industry-standard constraint, analysis, and reporting methodology. The Intel® Quartus® Prime software generates timing analysis data by default during design compilation.

Running timing analysis involves running the Compiler, specifying timing constraints, and viewing timing analysis reports. The following steps describe this process in detail.

Note: This Quick-Start requires a basic understanding of timing analysis concepts and the Intel® Quartus® Prime design flow, as the Intel® Quartus® Prime Pro Edition Foundation Online Training describes.
Figure 1. fir_filter Design Schematic
Level Two Title