Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683532
Date 8/05/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. AFU Design 3. OPAE Support 4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History
1. Introduction x
1.1. How to Use this Guide
2. AFU Design x
2.1. HSSI Device Interface 2.2. Connecting the MAC to the HSSI PHY 2.3. Verifying Network Port Function
2.1. HSSI Device Interface x
2.1.1. HSSI Clocks 2.1.2. HSSI Unified Data Interface 2.1.3. HSSI PHY Control and Status 2.1.4. HSSI PR Management 2.1.5. HSSI Reset Control and Status 2.1.6. Initialization
2.2. Connecting the MAC to the HSSI PHY x
2.2.1. 4x10GBASE-SR Mode 2.2.2. 40GBASE-SR4 Mode
2.2.1. 4x10GBASE-SR Mode x
2.2.1.1. Clocks in 4x10GBASE-SR Mode 2.2.1.2. Unified Data Interface in 4x10GBASE-SR Mode 2.2.1.3. PHY Control and Status in 4x10GBASE-SR Mode 2.2.1.4. PR Management in 4x10GBASE-SR Mode 2.2.1.5. Reset Control and Status in 4x10GBASE-SR Mode 2.2.1.6. Initialization in 4x10GBASE-SR Mode 2.2.1.7. Unused 10GbE Channels
2.2.2. 40GBASE-SR4 Mode x
2.2.2.1. Clocks in 40GBASE-SR4 Mode 2.2.2.2. Unified Data Interface in 40GBASE-SR4 Mode 2.2.2.3. PHY Control and Status in 40GBASE-SR4 Mode 2.2.2.4. PR Management in 40GBASE-SR4 Mode 2.2.2.5. Reset Control and Status in 40GBASE-SR4 Mode 2.2.2.6. Initialization in 40GBASE-SR4 Mode
3. OPAE Support x
3.1. OPAE Driver HSSI sysfs Files 3.2. Managing the Network Port
3.1. OPAE Driver HSSI sysfs Files x
3.1.1. The board_id sysfs 3.1.2. The eeprom sysfs 3.1.3. The config sysfs 3.1.4. The equalizer_tune sysfs
3.1.4. The equalizer_tune sysfs x
3.1.4.1. Receiver CTLE AC Gain sysfs Encodings 3.1.4.2. Receiver VGA sysfs Encodings 3.1.4.3. Receiver CTLE DC Gain sysfs Encodings 3.1.4.4. Transmitter Pre-Emphasis First Post Tap Encodings 3.1.4.5. Transmitter Pre-Emphasis Second Post Tap Encodings 3.1.4.6. Transmitter Pre-Emphasis First Pre Tap Encodings 3.1.4.7. Transmitter Pre-Emphasis Second Pre Tap Encodings 3.1.4.8. Transmitter VOD Encodings
3.2. Managing the Network Port x
3.2.1. Configuring the Network Port 3.2.2. Reading the Base MAC Address from the Intel® PAC with Intel® Arria® 10 GX FPGA 3.2.3. Modifying HSSI PHY Transceiver PMA Settings
3.2.3. Modifying HSSI PHY Transceiver PMA Settings x
3.2.3.1. HSSI PHY Analog PMA Presets
1. Introduction
2. AFU Design
3. OPAE Support
4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History

2.1.2. HSSI Unified Data Interface

The HSSI unified data interface conforms to the Arria 10 FPGA Transceiver Native PHY IP with enhanced PCS. It consists of generic parallel data and encoding control interfaces for transmit and receive that are mapped to specific signaling behavior based on the configured HSSI PHY mode. The unified data interface also includes flow control ports to manage passing data to and from the HSSI PHY.

The below table provides a cross reference from the hssi:raw_pr unified data interface signals to the Arria 10 FPGA Transceiver Native PHY IP with enhanced PCS signal set. For detailed information on these signals, see the Intel Arria 10 Transceiver PHY User Guide as referenced in the below table.

Table 3.  HSSI Unified Data Interface

hssi Port Name

Width

Direction

Clock Domain

Native PHY IP Port Name

Reference in Intel Arria 10 Transceiver PHY User Guide

Transmit and Receive Data and Encoding Control Ports

a2f_tx_parallel_data

(4*128)

Input

f2a_tx_clk

tx_parallel_data

Table Enhanced TX PCS: Parallel Data, Control, and Clocks in Enhanced PCS Ports

a2f_tx_control

(4*18)

Input

f2a_tx_clk

tx_control

f2a_rx_parallel_data

(4*128)

Output

f2a_rx_clk_ln0

rx_parallel_data

f2a_rx_control

(4*20)

Output

f2a_rx_clk_ln0

rx_control

Flow Control Ports

f2a_tx_enh_fifo_full

4

Output

f2a_tx_clk

tx_enh_fifo_full

Table Enhanced PCS TX FIFO in Enhanced PCS Ports

f2a_tx_enh_fifo_pfull

4

Output

f2a_tx_clk

tx_enh_fifo_pfull

f2a_tx_enh_fifo_empty

4

Output

f2a_tx_clk

tx_enh_fifo_empty

f2a_tx_enh_fifo_pempty

4

Output

f2a_tx_clk

tx_enh_fifo_pempty

a2f_tx_enh_data_valid

4

Input

f2a_tx_clk

tx_enh_data_valid

f2a_rx_enh_fifo_full

4

Output

f2a_rx_clk_ln0

rx_enh_fifo_full

Table Enhanced PCS RX FIFO in Enhanced PCS Ports

f2a_rx_enh_fifo_pfull

4

Output

f2a_rx_clk_ln0

rx_enh_fifo_pfull

f2a_rx_enh_fifo_empty

4

Output

f2a_rx_clk_ln0

rx_enh_fifo_empty

f2a_rx_enh_fifo_pempty

4

Output

f2a_rx_clk_ln0

rx_enh_fifo_pempty

f2a_rx_enh_data_valid

4

Output

f2a_rx_clk_ln0

rx_enh_data_valid

a2f_rx_enh_fifo_rd_en

4

Input

f2a_rx_clk_ln0

rx_enh_fifo_rd_en

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