Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683532
Date 8/05/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. AFU Design 3. OPAE Support 4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History
1. Introduction x
1.1. How to Use this Guide
2. AFU Design x
2.1. HSSI Device Interface 2.2. Connecting the MAC to the HSSI PHY 2.3. Verifying Network Port Function
2.1. HSSI Device Interface x
2.1.1. HSSI Clocks 2.1.2. HSSI Unified Data Interface 2.1.3. HSSI PHY Control and Status 2.1.4. HSSI PR Management 2.1.5. HSSI Reset Control and Status 2.1.6. Initialization
2.2. Connecting the MAC to the HSSI PHY x
2.2.1. 4x10GBASE-SR Mode 2.2.2. 40GBASE-SR4 Mode
2.2.1. 4x10GBASE-SR Mode x
2.2.1.1. Clocks in 4x10GBASE-SR Mode 2.2.1.2. Unified Data Interface in 4x10GBASE-SR Mode 2.2.1.3. PHY Control and Status in 4x10GBASE-SR Mode 2.2.1.4. PR Management in 4x10GBASE-SR Mode 2.2.1.5. Reset Control and Status in 4x10GBASE-SR Mode 2.2.1.6. Initialization in 4x10GBASE-SR Mode 2.2.1.7. Unused 10GbE Channels
2.2.2. 40GBASE-SR4 Mode x
2.2.2.1. Clocks in 40GBASE-SR4 Mode 2.2.2.2. Unified Data Interface in 40GBASE-SR4 Mode 2.2.2.3. PHY Control and Status in 40GBASE-SR4 Mode 2.2.2.4. PR Management in 40GBASE-SR4 Mode 2.2.2.5. Reset Control and Status in 40GBASE-SR4 Mode 2.2.2.6. Initialization in 40GBASE-SR4 Mode
3. OPAE Support x
3.1. OPAE Driver HSSI sysfs Files 3.2. Managing the Network Port
3.1. OPAE Driver HSSI sysfs Files x
3.1.1. The board_id sysfs 3.1.2. The eeprom sysfs 3.1.3. The config sysfs 3.1.4. The equalizer_tune sysfs
3.1.4. The equalizer_tune sysfs x
3.1.4.1. Receiver CTLE AC Gain sysfs Encodings 3.1.4.2. Receiver VGA sysfs Encodings 3.1.4.3. Receiver CTLE DC Gain sysfs Encodings 3.1.4.4. Transmitter Pre-Emphasis First Post Tap Encodings 3.1.4.5. Transmitter Pre-Emphasis Second Post Tap Encodings 3.1.4.6. Transmitter Pre-Emphasis First Pre Tap Encodings 3.1.4.7. Transmitter Pre-Emphasis Second Pre Tap Encodings 3.1.4.8. Transmitter VOD Encodings
3.2. Managing the Network Port x
3.2.1. Configuring the Network Port 3.2.2. Reading the Base MAC Address from the Intel® PAC with Intel® Arria® 10 GX FPGA 3.2.3. Modifying HSSI PHY Transceiver PMA Settings
3.2.3. Modifying HSSI PHY Transceiver PMA Settings x
3.2.3.1. HSSI PHY Analog PMA Presets
1. Introduction
2. AFU Design
3. OPAE Support
4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History

1.1. How to Use this Guide

There are two major components to enable using the network port feature on the Intel® PAC with Intel® Arria® 10 GX FPGA. First, the host must configure the HSSI PHY in the hardware platform’s FIM for one of the supported modes (4x10GBASE-SR or 40GBASE-SR4). Secondly, the host must load an accelerator function (AF) that supports the network port feature.

The AFU Design section covers the requirements in the AFU design to enable the network port feature. The section describes the network MAC and PHY components that must be implemented in the AFU design and how to connect them to the HSSI PHY in the FIM through the hssi device interface. This section also gives some guidance on verifying your AFU implementation for network port connectivity in hardware.

The OPAE Support section covers using the OPAE driver and tools to provision the network port feature from the host, including configuring the HSSI PHY for the desired mode of operation, loading a network-enabled AF, and retrieving information from the Intel® PAC with Intel® Arria® 10 GX FPGA such as MAC address.

This document was previously titled as HSSI User Guide for Intel Programmable Acceleration Card (PAC) Intel Arria 10 GX FPGA.

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