Networking Interface for Open Programmable Acceleration Engine: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683532
Date 8/05/2019
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. AFU Design 3. OPAE Support 4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History
1. Introduction x
1.1. How to Use this Guide
2. AFU Design x
2.1. HSSI Device Interface 2.2. Connecting the MAC to the HSSI PHY 2.3. Verifying Network Port Function
2.1. HSSI Device Interface x
2.1.1. HSSI Clocks 2.1.2. HSSI Unified Data Interface 2.1.3. HSSI PHY Control and Status 2.1.4. HSSI PR Management 2.1.5. HSSI Reset Control and Status 2.1.6. Initialization
2.2. Connecting the MAC to the HSSI PHY x
2.2.1. 4x10GBASE-SR Mode 2.2.2. 40GBASE-SR4 Mode
2.2.1. 4x10GBASE-SR Mode x
2.2.1.1. Clocks in 4x10GBASE-SR Mode 2.2.1.2. Unified Data Interface in 4x10GBASE-SR Mode 2.2.1.3. PHY Control and Status in 4x10GBASE-SR Mode 2.2.1.4. PR Management in 4x10GBASE-SR Mode 2.2.1.5. Reset Control and Status in 4x10GBASE-SR Mode 2.2.1.6. Initialization in 4x10GBASE-SR Mode 2.2.1.7. Unused 10GbE Channels
2.2.2. 40GBASE-SR4 Mode x
2.2.2.1. Clocks in 40GBASE-SR4 Mode 2.2.2.2. Unified Data Interface in 40GBASE-SR4 Mode 2.2.2.3. PHY Control and Status in 40GBASE-SR4 Mode 2.2.2.4. PR Management in 40GBASE-SR4 Mode 2.2.2.5. Reset Control and Status in 40GBASE-SR4 Mode 2.2.2.6. Initialization in 40GBASE-SR4 Mode
3. OPAE Support x
3.1. OPAE Driver HSSI sysfs Files 3.2. Managing the Network Port
3.1. OPAE Driver HSSI sysfs Files x
3.1.1. The board_id sysfs 3.1.2. The eeprom sysfs 3.1.3. The config sysfs 3.1.4. The equalizer_tune sysfs
3.1.4. The equalizer_tune sysfs x
3.1.4.1. Receiver CTLE AC Gain sysfs Encodings 3.1.4.2. Receiver VGA sysfs Encodings 3.1.4.3. Receiver CTLE DC Gain sysfs Encodings 3.1.4.4. Transmitter Pre-Emphasis First Post Tap Encodings 3.1.4.5. Transmitter Pre-Emphasis Second Post Tap Encodings 3.1.4.6. Transmitter Pre-Emphasis First Pre Tap Encodings 3.1.4.7. Transmitter Pre-Emphasis Second Pre Tap Encodings 3.1.4.8. Transmitter VOD Encodings
3.2. Managing the Network Port x
3.2.1. Configuring the Network Port 3.2.2. Reading the Base MAC Address from the Intel® PAC with Intel® Arria® 10 GX FPGA 3.2.3. Modifying HSSI PHY Transceiver PMA Settings
3.2.3. Modifying HSSI PHY Transceiver PMA Settings x
3.2.3.1. HSSI PHY Analog PMA Presets
1. Introduction
2. AFU Design
3. OPAE Support
4. Networking Interface for Open Programmable Acceleration Engine: Intel® PAC with Intel® Arria® 10 GX FPGA Revision History

2.2.2.1. Clocks in 40GBASE-SR4 Mode

The hssi interface provides a set of clocks and locked status flags to support 40GbE MAC/PCS IP. The interface provides 312.5MHz clock sources for both transmit and receive datapaths. The 40-bit interface between the MAC/PHY and HSSI PHY is synchronous to f2a_tx_clk and f2a_rx_clk_ln0 for transmit and receive, respectively. The locked status outputs from the fPLLs in the HSSI PHY can be used by the MAC and related AFU logic as needed. The additional set of 312.5MHz clock sources (e.g., f2a_tx_clkx2, f2a_rx_clkx2_ln0) are phase-aligned replications and would typically not be needed by the MAC/PHY and related AFU logic.

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