FIFO Intel® FPGA IP User Guide

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ID 683522
Date 7/08/2024
Public
Document Table of Contents
Document Table of Contents x
1. FIFO Intel® FPGA IP User Guide
1. FIFO Intel® FPGA IP User Guide x
1.1. Configuration Methods 1.2. Specifications 1.3. FIFO Functional Timing Requirements 1.4. SCFIFO ALMOST_EMPTY Functional Timing 1.5. FIFO Output Status Flag and Latency 1.6. FIFO Metastability Protection and Related Options 1.7. FIFO Synchronous Clear and Asynchronous Clear Effect 1.8. SCFIFO and DCFIFO Show-Ahead Mode 1.9. Different Input and Output Width 1.10. DCFIFO Timing Constraint Setting 1.11. Coding Example for Manual Instantiation 1.12. Design Example 1.13. Gray-Code Counter Transfer at the Clock Domain Crossing 1.14. Guidelines for Embedded Memory ECC Feature 1.15. FIFO Intel® FPGA IP User Guide Archives 1.16. Document Revision History for the FIFO Intel® FPGA IP User Guide
1.2. Specifications x
1.2.1. Verilog HDL Prototype 1.2.2. VHDL Component Declaration 1.2.3. VHDL LIBRARY-USE Declaration 1.2.4. FIFO Signals 1.2.5. FIFO Parameter Settings
1.7. FIFO Synchronous Clear and Asynchronous Clear Effect x
1.7.1. Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO
1.10. DCFIFO Timing Constraint Setting x
1.10.1. Embedded Timing Constraint 1.10.2. User Configurable Timing Constraint
1.10.2. User Configurable Timing Constraint x
1.10.2.1. SDC Commands
1. FIFO Intel® FPGA IP User Guide

1.10.2.1. SDC Commands

Table 14.  SDC Commands usage in the Quartus® Prime Fitter and Timing Analyzer These SDC descriptions provided are overview for DCFIFO use case. For the exact SDC details, refer to the Quartus® Prime Timing Analyzer chapter in the Quartus® Prime Pro Edition Handbook.
SDC Command Fitter Timing Analyzer Recommended Settings
set_max_skew 27 To constraint placement and routing of flops in the multi-bit CDC paths to meet the specified skew requirement among bits.

To analyze whether the specified skew requirement is fully met. Both clock and data paths are taken into consideration.

Set to less than 1 launch clock.
set_net_delay

Similar to set_max_skew but without taking clock skews into considerations.

To ensure the crossing latency is bounded.

To analyze whether the specified net delay requirement is fully met. Clock paths are not taken into consideration.

This is currently set to be less than 1 latch clock. 28

set_min_delay/set_max_delay

To relax fitter effort by mimicking the set_false_path command but without overriding other SDCs. 29

To relax timing analysis for the setup/hold checks to not fail. 30

This is currently set to 100ns/-100ns for max/min. 31

Related Information
27 It can have significant compilation time impact in older Quartus versions without Timing Analyzer 2.
28 For advanced users, you can fine-tune the value based on your design. For instance, if the designs are able to tolerate longer crossing latency (full and empty status can be delayed), this can be relaxed.
29 Without set_false_path (which has the highest precedence and may result in very long insertion delays), Fitter attempts to meet the default setup/hold which is extremely over constraint.
30 Without set_false_path, the CDC paths will be analyzed for default setup/hold, which is extremely over constraint.
31 Expect an approximately 100 ns delay when you observe CDC paths compared to set_false_path.
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