Multi Channel DMA for PCI Express* Intel® FPGA IP Design Example User Guide

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ID 683517
Date 9/15/2021
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Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Design Example Detailed Description 3. Design Example Quick Start Guide 4. Multi Channel DMA for FPGA IP Design Example User Guide Archives 5. Document Revision History for the Multi Channel DMA for FPGA IP Design Example User Guide
2. Design Example Detailed Description x
2.1. Design Example Overview 2.2. Hardware and Software Requirements 2.3. PIO Using MCDMA Bypass Mode 2.4. Avalon-ST Packet Generate/Check 2.5. Avalon-ST Device-side Packet Loopback 2.6. Avalon-MM DMA
2.3. PIO Using MCDMA Bypass Mode x
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode 2.3.2. Avalon-MM PIO Using MCDMA Bypass mode
2.3.1. Avalon-ST PIO Using MCDMA Bypass Mode x
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode 2.3.1.2. Single-Port Avalon-ST PIO Using MCDMA Bypass Mode
2.3.1.1. Four-Port Avalon-ST PIO Using MCDMA Bypass Mode x
2.3.1.1.1. Simulation Result 2.3.1.1.2. Hardware Test Result
2.3.2. Avalon-MM PIO Using MCDMA Bypass mode x
2.3.2.1. Simulation Results 2.3.2.2. Hardware Test Results
2.4. Avalon-ST Packet Generate/Check x
2.4.1. Four-Port Avalon-ST Packet Generate/Check 2.4.2. Single-Port Avalon-ST Packet Generate/Check
2.4.1. Four-Port Avalon-ST Packet Generate/Check x
2.4.1.1. Simulation Results 2.4.1.2. Hardware Test Results
2.4.2. Single-Port Avalon-ST Packet Generate/Check x
2.4.2.1. Simulation Waveforms 2.4.2.2. Simulation Log
2.5. Avalon-ST Device-side Packet Loopback x
2.5.1. Simulation Results 2.5.2. Hardware Test Results
2.6. Avalon-MM DMA x
2.6.1. Simulation Results 2.6.2. Hardware Test Results
3. Design Example Quick Start Guide x
3.1. Design Example Directory Structure 3.2. Generating the Example Design using Intel® Quartus® Prime 3.3. Simulating the Design Example 3.4. Compiling the Example Design in Intel® Quartus® Prime 3.5. Running the Design Example Application on a Hardware Setup
3.2. Generating the Example Design using Intel® Quartus® Prime x
3.2.1. Procedure
3.3. Simulating the Design Example x
3.3.1. Testbench Overview 3.3.2. Example Testbench Flow for DMA Test with Avalon-ST Packet Generate/Check Design Example 3.3.3. Run the Simulation Script 3.3.4. View the Results
3.5. Running the Design Example Application on a Hardware Setup x
3.5.1. Program the FPGA 3.5.2. Quick Start Guide
3.5.2. Quick Start Guide x
3.5.2.1. Software Test Setup 3.5.2.2. Driver Support 3.5.2.3. MCDMA Custom Driver 3.5.2.4. MCDMA DPDK Poll Mode Driver 3.5.2.5. MCDMA Kernel Mode Driver
3.5.2.3. MCDMA Custom Driver x
3.5.2.3.1. Prerequisites 3.5.2.3.2. Software Setup 3.5.2.3.3. Run the Reference Example Application
3.5.2.3.1. Prerequisites x
3.5.2.3.1.1. Configuration Changes from BIOS 3.5.2.3.1.2. External Packages 3.5.2.3.1.3. Set the Boot Parameters
3.5.2.3.2. Software Setup x
3.5.2.3.2.1. Installing the Linux Kernel Driver and Enabling VFs 3.5.2.3.2.2. Build and Install User Space Library 3.5.2.3.2.3. Create Guest VM by Using QEMU 3.5.2.3.2.4. Establish Communication Between Host and QEMU
3.5.2.3.3. Run the Reference Example Application x
3.5.2.3.3.1. Meta Data Test 3.5.2.3.3.2. BAM Test 3.5.2.3.3.3. Packet Gen Test
3.5.2.4. MCDMA DPDK Poll Mode Driver x
3.5.2.4.1. Prerequisites 3.5.2.4.2. Install PMD and Test Application 3.5.2.4.3. Run the Reference Example Application
3.5.2.4.1. Prerequisites x
3.5.2.4.1.1. Set the Boot Parameters 3.5.2.4.1.2. Configuration Changes from BIOS 3.5.2.4.1.3. Install and Build Testpmd
3.5.2.4.2. Install PMD and Test Application x
3.5.2.4.2.1. Create VM Environment
3.5.2.5. MCDMA Kernel Mode Driver x
3.5.2.5.1. Prerequisites 3.5.2.5.2. Software Setup 3.5.2.5.3. Examples
3.5.2.5.1. Prerequisites x
3.5.2.5.1.1. Host Configuration 3.5.2.5.1.2. Set the Boot Parameters
3.5.2.5.2. Software Setup x
3.5.2.5.2.1. Build and Install Kernel Driver 3.5.2.5.2.2. Build and Install Libmcmem 3.5.2.5.2.3. Build Testapp 3.5.2.5.2.4. Configure Kernel Driver 3.5.2.5.2.5. Configure Libmcmem 3.5.2.5.2.6. Configure Testapp
1. Terms and Acronyms
2. Design Example Detailed Description
3. Design Example Quick Start Guide
4. Multi Channel DMA for FPGA IP Design Example User Guide Archives
5. Document Revision History for the Multi Channel DMA for FPGA IP Design Example User Guide

2.1. Design Example Overview

The Multi Channel DMA for PCI Express IP Design Examples demonstrate a Multi Channel DMA solution for Intel® Stratix® 10 GX/MX devices using the H-Tile PCIe Gen3 hard IP, Intel® Stratix® 10 DX and Intel® Agilex™ devices using the P-Tile PCIe Gen4 Hard IP and soft IP implemented in the FPGA fabric.

You can generate the design example from the Example Designs tab of the Multi Channel DMA for PCI Express IP Parameter Editor. The desired user interface type, either Avalon-ST or Avalon-MM, can be chosen. You can allocate up to 2048 DMA channels (with a maximum of 512 channels per function) when the Avalon-MM Interface type is selected. For the Avalon-ST 4-port Interface, one channel is allocated per port. For the Avalon-ST 1-port interface, you can allocate up to 256 channels in both H-Tile and P-Tile variants. You can also configure the PCIe BAR2 size that is mapped to the Avalon-MM PIO Master port.

Table 2.  Supported Design Example Configurations for H-tile The Hard IP Modes supported are Gen3 x16, 512-bit/Gen3 x8, 256-bit
Design Example User Mode Interface Type Number of Ports Total Channels Supported SR-IOV Support Simulation Synthesis Driver Support
Avalon-MM DMA Multi channel DMA Avalon-MM 1 Up to 2K 2 No Up to 2K channels Up to 2K channels
  • Custom
  • DPDK
  • Kernel Mode
Avalon-MM DMA Multi channel DMA 1 Up to 2K 2 Yes 1 Physical Function and its Virtual Functions Up to 2K channels
  • Custom
  • DPDK
Device-side Packet Loopback Multi channel DMA Avalon-ST 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 4 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 No Up to 256 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 1 Up to 256 No Up to 256 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 1 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 Yes 1 Physical Function and its Virtual Functions Up to 256 channels
  • Custom
  • DPDK
Packet Generate / Check Multi channel DMA 1 Up to 256 Yes 1 Physical Function and its Virtual Functions Up to 256 channels
  • Custom
  • DPDK
PIO using MQDMA Bypass Mode Bursting Master Avalon-MM N/A N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Table 3.  Supported Design Example Configurations for P-tile The Hard IP Modes supported are Gen4 x16, 512-bit/Gen4 x8, 256-bit/Gen3 x16, 512-bit/Gen3 x8, 256-bit
Design Example User Mode Interface Type Number of Ports Total Channels Supported SR-IOV Support Simulation Synthesis Driver Support3
Avalon-MM DMA Multi channel DMA Avalon-MM 1 Up to 2K 2 No Up to 2K channels Up to 2K channels
  • Custom
  • DPDK
  • Kernel Mode
Avalon-MM DMA Multi channel DMA 1 Up to 2K 2 Yes Not supported Up to 2K channels
  • Custom
  • DPDK
Device-side Packet Loopback Multi channel DMA Avalon-ST 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 4 4 No 1 channel per port 1 channel per port
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 4 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 No Up to 64 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
Packet Generate / Check Multi channel DMA 1 Up to 256 No Up to 64 channels Up to 256 channels
  • Custom
  • DPDK
  • Kernel Mode
PIO using MQDMA Bypass Mode Multi channel DMA 1 N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
Device-side Packet Loopback Multi channel DMA 1 Up to 256 Yes 4 Not supported Up to 256 channels
  • Custom
  • DPDK
Packet Generate / Check Multi channel DMA 1 Up to 256 Yes 4 Not supported Up to 256 channels
  • Custom
  • DPDK
PIO using MQDMA Bypass Mode Bursting Master Avalon-MM N/A N/A No Yes Yes
  • Custom
  • DPDK
  • Kernel Mode
1 Custom driver is used to generate hardware test results in this document. Every hardware test result is based on the perfq_app command.
2 512 channels per function
3 Custom driver is used to generate hardware test results in this document. Every hardware test result is based on the perfq_app command.
4 Refer to P-tile Avalon Streaming Intel FPGA IP for PCI Express User Guide for supported physical function or virtual function combinations.
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