AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

Download PDF
ID 683511
Date 5/28/2019
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 890: JESD204B Intel FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix 10 L-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices

1.3.1.2. Initial Frame and Lane Synchronization

Table 2.  Initial Frame and Lane Synchronization Test Cases
Test Case Objective Description Passing Criteria

ILA.1

 Check that the /R/ and /A/ characters are transmitted at the beginning and end of each multiframe. Verify that four multiframes are transmitted in the ILAS phase and the receiver detects the initial lane alignment sequence correctly.
The following signals in <ip_variant_name>_inst_phy.v are tapped:
  • jesd204_tx_pcs_data[(L*32)-1..0]
  • jesd204_tx_pcs_kchar_data[(L*4)-1..0] 2
The following signals in <ip_variant_name>.v are tapped:
  • sync_n
  • jesd204_tx_int

The txlink_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

Each lane is represented by a 32-bit data bus for the jesd204_tx_pcs_data signal. The 32-bit data bus is divided into four octets.

Check for the following status in the AD9174 registers:
  • Frame Synchronization
  • Initial Lane Synchronization
  • The /R/ character or K28.0 (0x1C) is transmitted at the jesd204_tx_pcs_data bus to mark the beginning of each multiframe.
  • The /A/ character or K28.3 (0x7C) is transmitted at the jesd204_tx_pcs_data bus to mark the end of each multiframe.
  • The sync_n and jesd204_tx_int signals are deasserted.
  • The jesd204_rx_pcs_kchar_data signal is asserted whenever control characters such as the /K/, /R/, /Q/, or /A/ characters are transmitted.
  • The "Frame Synchronization" and "Initial Lane Synchronization" status for all lanes are asserted in the AD9174 registers 0x471 and 0x473, respectively.

ILA.2

 Check that the JESD204B configuration parameters are transmitted in the second multiframe.
The following signal in <ip_variant_name>_inst_phy.v is tapped:
  • jesd204_tx_pcs_data[(L*32)-1..0] 2
The following signal in <ip_variant_name>.v is tapped:
  • jesd204_tx_int

The txlink_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

The system console accesses the following registers:
  • ilas_data1
  • ilas_data2

The content of 14 configuration octets in the second multiframe is stored in the above 32-bit registers.

Check for the following status and error in the AD9174 registers:
  • Good Checksum
  • Configuration Mismatch Error
  • The /R/ character is followed by the /Q/ character or K28.4 (0x9C) in the jesd204_tx_pcs_data signal at the beginning of the second multiframe.
  • The jesd204_tx_int signal is deasserted if there is no error.
  • The JESD204B parameters read from the ilas_data1 and ilas_data2 registers are the same as the parameters set in the JESD204B Intel® FPGA IP Platform Designer component editor.
  • The “Good Checksum” status is asserted in the AD9174 register 0x472.
  • “Link Configuration Mismatch Error” is not asserted in the AD9174 register 0x4BB.

ILA.3

 Check the constant pattern of the transmitted user data after the end of the fourth multiframe. Verify that the receiver successfully enters user data phase.
The following signal in <ip_variant_name>_inst_phy.v is tapped:
  • jesd204_tx_pcs_data[(L*32)-1..0] 2
The following signal in <ip_variant_name>.v is tapped:
  • jesd204_tx_int

The txlink_clk signal is used as the sampling clock for the Signal Tap logic analyzer.

The system console accesses the JESD configuration and status register (CSR) tx_err.

Check for the following errors in the AD9174 registers:
  • Lane FIFO Full
  • Lane FIFO Empty
  • When the scrambler is turned off, the first user data is transmitted after the last /A/ character, which marks the end of the fourth multiframe transmitted.3
  • Bits 2 and 3 of the JESD tx_err register are not set to “1”.
  • The “Lane FIFO Full” and “Lane FIFO Empty” errors are not asserted in the AD9174 registers 0x30C and 0x30D, respectively.
  • The jesd204_tx_int signal is deasserted if there is no error.
2 L is the number of lanes.
3 When the scrambler is turned on, the data pattern cannot be recognized after the fourth multiframe in the ILAS phase.
Level Two Title