AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

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ID 683511
Date 5/28/2019
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 890: JESD204B Intel FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix 10 L-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices

1.3.4. Deterministic Latency (Subclass 1)

The following figure shows the block diagram of the deterministic latency test setup. The HMC7044 clock generator in the AD9174 EVM provides periodic SYSREF pulses for both the DAC and JESD204B Intel® FPGA IP.

Figure 4. Deterministic Latency Test Setup Block Diagram

The FPGA generates a 16-bit digital sample with a value of 8000 (hexadecimal) at the transport layer. The most-significant bit of this digital sample has a logic 1 value. This bit is routed out from the FPGA and probed at channel 1 of the oscilloscope. The DAC analog channel is probed at channel 2 of the oscilloscope. The time difference between the pulses at channel 1 (t0) and channel 2 (t1) is measured. This time difference represents the total latency of the JESD204B link, DAC digital blocks, and analog channel.

Table 5.  Deterministic Latency Test Cases
Test Case Objective Description Passing Criteria
DL.1

Measure the total latency.

Measure the time difference between the rising edge of pulses at channels 1 and 2 of the oscilloscope.

Latency is consistent.
DL.2

Re-measure the total latency after the DAC power cycle and FPGA reconfiguration.

Measure the time difference between the rising edge of pulses at channels 1 and 2 of the oscilloscope.

Latency is consistent.
Level Two Title