AN 890: JESD204B Intel® FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix® 10 L-Tile Devices

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ID 683511
Date 5/28/2019
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Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices x
1.1. Hardware Requirements 1.2. Hardware Setup 1.3. Hardware Checkout Methodology 1.4. JESD204B Intel FPGA IP and DAC Configurations 1.5. Test Results 1.6. Test Result Comments 1.7. Document Revision History for AN 890: JESD204B Intel FPGA IP and ADI AD9174 Interoperability Report for Intel Stratix 10 L-Tile Devices 1.8. Appendix
1.3. Hardware Checkout Methodology x
1.3.1. Transmitter Data Link Layer 1.3.2. Transmitter Transport Layer 1.3.3. Scrambling 1.3.4. Deterministic Latency (Subclass 1)
1.3.1. Transmitter Data Link Layer x
1.3.1.1. Code Group Synchronization 1.3.1.2. Initial Frame and Lane Synchronization
1. JESD204B Intel® FPGA IP and ADI AD9174 Hardware Checkout Report for Intel Stratix® 10 Devices

1.2. Hardware Setup

An Intel® Stratix® 10 GX Signal Integrity Development Kit (ES Edition) is used with the ADI AD9174 daughter card module installed to the development board’s FMC+ connector.

  • The AD9174 EVM derives power from the FMC+ pins.
  • The FPGA clock is supplied by a Silicon Labs Si5341 clock generator on the development kit.
  • The Si5341 clock generator provides a reference clock to the HMC7044 clock generator in the AD9174 EVM through an SMA cable. The phase-locked loop (PLL) in the AD9174 device generates the desired sampling clock.
  • For subclass 1, the HMC7044 clock generator in the AD9174 EVM provides the SYSREF for the FPGA as well as the AD9174 device.
  • The sync_n signal is transmitted from the DAC to the FPGA through the FMC+ pins.
Figure 1. Hardware Setup
Figure 2. System DiagramThis system-level diagram shows how the different modules connect.

In this setup, where LMF = 821, the data rate of the transceiver lanes is 14.7456 Gbps. The HMC7044 clock generator in the AD9174 EVM provides SYSREF for both the FPGA and DAC. It also provides the reference clock to the DAC PLL to generate the desired DAC sample rate of 11796.48 Msps. The AD9174 DAC provides the sync_n signal through the FMC+ pins. The AD9174 DAC can operate in single or dual JESD links. The HMC7044 clock generator and DAC are programmed by the FPGA through the serial peripheral interface (SPI).

Level Two Title