AN 869: Partially Reconfiguring a Design: on Intel® Cyclone® 10 GX FPGA Development Board

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ID 683503
Date 7/15/2019
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 869: Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration Controller IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 9: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board

Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board

Updated for:
Intel® Quartus® Prime Design Suite 19.1
This application note demonstrates transforming a simple design into a partially reconfigurable design and implementing the design on the Intel® Cyclone® 10 GX FPGA development board.

The partial reconfiguration (PR) feature allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function. You can create multiple personas for a particular region in your design, without impacting operation in areas outside this region. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. The current version of the software introduces a new and simplified compilation flow for partial reconfiguration.

Partial reconfiguration has the following advantages over a flat design:
  • Allows run-time design reconfiguration
  • Increases scalability of the design
  • Reduces system down-time
  • Supports dynamic time-multiplexing functions in the design
  • Lowers cost and power consumption through efficient use of board space

Implementation of this reference design requires basic familiarity with the Intel® Quartus® Prime FPGA implementation flow and knowledge of the primary Intel® Quartus® Prime project files.

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