AN 869: Partially Reconfiguring a Design: on Intel® Cyclone® 10 GX FPGA Development Board

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ID 683503
Date 7/15/2019
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 869: Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration Controller IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 9: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board

Step 9: Programming the Board

Before you begin:
  1. Connect the power supply to the Intel® Cyclone® 10 GX FPGA development board.
  2. Connect the Intel® FPGA Download Cable between your PC USB port and the Intel® FPGA Download Cable port on the development board.
Note: This tutorial utilizes the Intel® Cyclone® 10 GX FPGA development board on the bench, outside of the PCIe* slot in your host machine.

To run the design on the Intel® Cyclone® 10 GX FPGA development board:

  1. Open the Intel® Quartus® Prime software and click Tools > Programmer.
  2. In the Programmer, click Hardware Setup and select an Intel FPGA download cable.
  3. Click Auto Detect and select the device, 10CX220YF.
  4. Click OK. The Intel® Quartus® Prime software detects and updates the Programmer with the three FPGA chips on the board.
  5. Select the 10CX220YF device, click Change File and load the blinking_led_default.sof file.
  6. Enable Program/Configure for blinking_led_default.sof file.
  7. Click Start and wait for the progress bar to reach 100%.
  8. Observe the LEDs on the board blinking at the same frequency as the original flat design.
  9. To program only the PR region, right-click the blinking_led_default.sof file in the Programmer and click Add PR Programming File.
  10. Select the blinking_led_default.pr_partition.rbf file.
  11. Disable Program/Configure for blinking_led_default.sof file.
  12. Enable Program/Configure for blinking_led_slow.pr_partition.rbf file and click Start. On the board, observe LED[0] and LED[1] continuing to blink. When the progress bar reaches 100%, LED[2] and LED[3] blink slower.
  13. To re-program the PR region, right-click the .rbf file in the Programmer and click Change PR Programing File.
  14. Select the .rbf files for the other two personas to observe the behavior on the board. Loading the blinking_led_default.pr_partition.rbf file causes the LEDs to blink at a specific frequency, and loading the blinking_led_empty.pr_partition.rbf file causes the LEDs to stay ON.
Figure 12. Programming the Intel® Cyclone® 10 GX FPGA Development Board
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