AN 869: Partially Reconfiguring a Design: on Intel® Cyclone® 10 GX FPGA Development Board

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ID 683503
Date 7/15/2019
Public
Document Table of Contents
Document Table of Contents x
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board x
Reference Design Requirements Reference Design Overview Reference Design Files Reference Design Walkthrough Document Revision History for AN 869: Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board
Reference Design Walkthrough x
Step 1: Getting Started Step 2: Creating a Design Partition Step 3: Allocating Placement and Routing Region for a PR Partition Step 4: Adding the Partial Reconfiguration Controller IP Step 5: Defining Personas Step 6: Creating Revisions Step 7: Compiling the Base Revision Step 8: Preparing PR Implementation Revisions Step 9: Programming the Board Modifying an Existing Persona Adding a New Persona to the Design
Step 4: Adding the Partial Reconfiguration Controller IP x
Updating the Top-Level Design
Step 6: Creating Revisions x
Setting the Base Revision Type Creating Implementation Revisions
Step 9: Programming the Board x
Troubleshooting PR Programming Errors
Partially Reconfiguring a Design on Intel® Cyclone® 10 GX FPGA Development Board

Reference Design Overview

This reference design consists of one 32-bit counter. At the board level, the design connects the clock to a 50 MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.

Figure 1. Flat Reference Design without PR Partitioning
Level Two Title