AN 320: Using Intel® FPGA IP Evaluation Mode

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ID 683502
Date 10/22/2018
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Document Table of Contents
Document Table of Contents x
1. AN 320: Using Intel® FPGA IP Evaluation Mode
1. AN 320: Using Intel® FPGA IP Evaluation Mode x
1.1. Intel® FPGA IP Evaluation Modes 1.2. Viewing IP Core License Status 1.3. Intel® FPGA IP Evaluation Mode Messages 1.4. Licensing Intel® FPGA IP Cores 1.5. Evaluation Period Timeout Indicator 1.6. Disable Intel® FPGA IP Evaluation Mode 1.7. Using Intel® FPGA IP Evaluation Mode in Teams ( Intel® Quartus® Prime Standard Edition) 1.8. Using Intel FPGA IP Evaluation Mode Document Revision History
1. AN 320: Using Intel® FPGA IP Evaluation Mode

1.1. Intel® FPGA IP Evaluation Modes

The Intel® FPGA IP Evaluation Mode supports the following two modes:
  • Tethered—Allows running the design containing the licensed IP indefinitely with a connection between your board and the host computer. Tethered mode requires a serial joint test action group (JTAG) cable connected between the JTAG port on your board and the host computer, which is running the Intel® Quartus® Prime Programmer for the duration of the hardware evaluation period. The Programmer only requires a minimum installation of the Intel® Quartus® Prime software, and requires no Intel® Quartus® Prime license. The host computer controls the evaluation time by sending a periodic signal to the device via the JTAG port. If all licensed IP cores in the design support tethered mode, the evaluation time runs until any IP core evaluation expires. If all of the IP cores support unlimited evaluation time, the device does not time-out.
  • Untethered—Allows running the design containing the licensed IP for a limited time. The IP core reverts to untethered mode if the device disconnects from the host computer running the Intel® Quartus® Prime software. The IP core also reverts to untethered mode if any other licensed IP core in the design does not support tethered mode.

When the evaluation time expires for any licensed IP in the design, the design stops functioning. All IP cores that use the Intel® FPGA IP Evaluation Mode time out simultaneously when any IP core in the design times out. When the evaluation time expires, you must reprogram the FPGA device before continuing hardware verification. To extend use of the IP core for production, purchase a full production license for the IP core.

Figure 1.  Intel® FPGA IP Evaluation Mode Flow
Note: Refer to each IP core's user guide for parameterization steps and implementation details.
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