AN 320: Using Intel® FPGA IP Evaluation Mode

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ID 683502
Date 10/22/2018
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Document Table of Contents
Document Table of Contents x
1. AN 320: Using Intel® FPGA IP Evaluation Mode
1. AN 320: Using Intel® FPGA IP Evaluation Mode x
1.1. Intel® FPGA IP Evaluation Modes 1.2. Viewing IP Core License Status 1.3. Intel® FPGA IP Evaluation Mode Messages 1.4. Licensing Intel® FPGA IP Cores 1.5. Evaluation Period Timeout Indicator 1.6. Disable Intel® FPGA IP Evaluation Mode 1.7. Using Intel® FPGA IP Evaluation Mode in Teams ( Intel® Quartus® Prime Standard Edition) 1.8. Using Intel FPGA IP Evaluation Mode Document Revision History
1. AN 320: Using Intel® FPGA IP Evaluation Mode

1.3. Intel® FPGA IP Evaluation Mode Messages

The Intel® Quartus® Prime Compiler generates messages about IP cores under Intel® FPGA IP Evaluation Mode. During compilation, the Compiler reports the soonest, untethered expiration time for all licensed Intel® FPGA IP cores in the design. The Compiler also reports the tethered mode evaluation time if all licensed Intel® FPGA IP cores in the design support tethered mode.
Figure 4. IP Evaluation Time Limit Messages
Note: The precise time of IP core evaluation timeout depends on the target FPGA device family and operating conditions.
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