1.8. Using Intel FPGA IP Evaluation Mode Document Revision History
This document has the following revision history:
Document Version | Intel® Quartus® Prime Version | Changes |
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2018.10.22 | 17.1.0 | Added Intel® Quartus® Prime Version column to Revision History Table. |
2017.11.06 | 17.1.0 |
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2017.07.15 | 17.0.0 |
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Date | Changes |
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2007.11.08 |
Added section on IP evaluation in teams. |
2007.09.15 | Removed references to unsupported Logic Lock (Standard) flow. |
2007.05.08 | Updated steps for disabling evaluation mode. |
2003.10.15 | Initial document release. |