AN 320: Using Intel® FPGA IP Evaluation Mode

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ID 683502
Date 10/22/2018
Public
Document Table of Contents
Document Table of Contents x
1. AN 320: Using Intel® FPGA IP Evaluation Mode
1. AN 320: Using Intel® FPGA IP Evaluation Mode x
1.1. Intel® FPGA IP Evaluation Modes 1.2. Viewing IP Core License Status 1.3. Intel® FPGA IP Evaluation Mode Messages 1.4. Licensing Intel® FPGA IP Cores 1.5. Evaluation Period Timeout Indicator 1.6. Disable Intel® FPGA IP Evaluation Mode 1.7. Using Intel® FPGA IP Evaluation Mode in Teams ( Intel® Quartus® Prime Standard Edition) 1.8. Using Intel FPGA IP Evaluation Mode Document Revision History
1. AN 320: Using Intel® FPGA IP Evaluation Mode

1.5. Evaluation Period Timeout Indicator

The Intel® Quartus® Prime software installation includes the ocp_timeout_indicator IP block in the libraries\others\opercore_plus\ directory. You can instantiate this IP block in your design to alert when the device times out.

Specify either an active_high or active_low polarity of the time-out signal (ip_timeout) with the timeout_indicator parameter.

Figure 5. OCP_TIMEOUT_INDICATOR IP Block Symbol

Timeout Indicator VHDL Component Declaration

component ocp_timeout_indicator is
generic
(
TIMEOUT_INDICATOR: string := "ACTIVE_HIGH"
);
port
(
ip_timeout: out std_logic
);
end component ocp_timeout_indicator;

Timeout Indicator VHDL Instantiation Prototype

My_Instance : ocp_timeout_indicator
GENERIC MAP(TIMEOUT_INDICATOR => "ACTIVE_HIGH")
PORT MAP(ip_timeout => My_Output);

Timeout Indicator Verilog HDL Instantiation Prototype

ocp_timeout_indicator my_instance
(.ip_timeout(my_output));
defparam my_instance.TIMEOUT_INDICATOR =
"ACTIVE_HIGH";
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