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Ixiasoft
1.5. Performance and Resource Utilization
The following table shows the recommended FPGA fabric speed grades for all the configurations that the R-tile Avalon® streaming IP core supports.
Configuration |
Application Clock Frequency (MHz) | Recommended FPGA Fabric Speed Grades |
Note |
---|---|---|---|
Gen5 1x16 EP/RP/BP | 400/425/450/475/500 | -1, -2 | |
Gen4 1x16 EP/RP/BP | 250/275/300 | -1, -2, -3 | |
400/425/450/475/500 |
-1, -2 | (*) | |
Gen3 1x16 EP/RP/BP | 250/275/300 | -1, -2, -3 | |
400/425/450/475/500 | -1, -2 | (*) | |
Gen5 2x8 EP/RP/BP | 400/425/450/475/500 | -1, -2 | |
Gen4 2x8 EP/RP/BP | 250/275/300 | -1, -2, -3 | |
400/425/450/475/500 |
-1, -2 | (*) | |
Gen3 2x8 EP/RP/BP | 250/275/300 | -1, -2, -3 | |
250/275/300 | -1, -2, -3 | (*) | |
Gen5 4x4 EP/RP/BP | 400/425/450/475/500 | -1, -2 | |
Gen4 4x4 EP/RP/BP | 400/425/450/475/500 | -1, -2 | |
400/425/450/475/500 | -1, -2 | (*) | |
Gen3 4x4 EP/RP/BP | 250/275/300 | -1, -2, -3 | |
250/275/300 | -1, -2, -3 | (*) | |
PIPE Direct |
500 | -1, -2 |
The following table shows the typical resource utilization information for selected configurations.
The resource usage is based on the Avalon® streaming IP core top-level entity (intel_rtile_pcie_ast) that includes IP core soft logic implemented in the FPGA fabric.
Link Configuration | Device Family | ALMs | M20Ks | Dedicated Logic Registers |
---|---|---|---|---|
Gen5 x16 | Intel® Agilex™ | 11721 | 0 | 32819 |
Gen4 x16 | Intel® Agilex™ | 11617 | 0 | 28127 |
Gen3 x16 | Intel® Agilex™ | 11617 | 0 | 28127 |
16-channel PIPE Direct | Intel® Agilex™ | 2257 | 0 | 1836 |
For more details on the R-tile Avalon® Streaming design example, refer to R-tile Avalon Streaming Intel FPGA IP for PCI Express Design Example User Guide.