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1. About the R-tile Avalon® Streaming Intel® FPGA IP for PCI Express
2. IP Architecture and Functional Description
3. Advanced Features
4. Interfaces
5. Parameters
6. Troubleshooting/Debugging
7. R-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide Archives
8. Document Revision History for the R-tile Avalon® Streaming Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
B. Root Port Enumeration
C. Implementation of Address Translation Services (ATS) in Endpoint Mode
D. Packets Forwarded to the User Application in TLP Bypass Mode
3.2.2.5.1. VirtIO Common Configuration Capability Register (Address: 0x012)
3.2.2.5.2. VirtIO Common Configuration BAR Indicator Register (Address: 0x013)
3.2.2.5.3. VirtIO Common Configuration BAR Offset Register (Address: 0x014)
3.2.2.5.4. VirtIO Common Configuration Structure Length Register (Address 0x015)
3.2.2.5.5. VirtIO Notifications Capability Register (Address: 0x016)
3.2.2.5.6. VirtIO Notifications BAR Indicator Register (Address: 0x017)
3.2.2.5.7. VirtIO Notifications BAR Offset Register (Address: 0x018)
3.2.2.5.8. VirtIO Notifications Structure Length Register (Address: 0x019)
3.2.2.5.9. VirtIO Notifications Notify Off Multiplier Register (Address: 0x01A)
3.2.2.5.10. VirtIO ISR Status Capability Register (Address: 0x02F)
3.2.2.5.11. VirtIO ISR Status BAR Indicator Register (Address: 0x030)
3.2.2.5.12. VirtIO ISR Status BAR Offset Register (Address: 0x031)
3.2.2.5.13. VirtIO ISR Status Structure Length Register (Address: 0x032)
3.2.2.5.14. VirtIO Device Specific Capability Register (Address: 0x033)
3.2.2.5.15. VirtIO Device Specific BAR Indicator Register (Address: 0x034)
3.2.2.5.16. VirtIO Device Specific BAR Offset Register (Address 0x035)
3.2.2.5.17. VirtIO Device Specific Structure Length Register (Address: 0x036)
3.2.2.5.18. VirtIO PCI Configuration Access Capability Register (Address: 0x037)
3.2.2.5.19. VirtIO PCI Configuration Access BAR Indicator Register (Address: 0x038)
3.2.2.5.20. VirtIO PCI Configuration Access BAR Offset Register (Address: 0x039)
3.2.2.5.21. VirtIO PCI Configuration Access Structure Length Register (Address: 0x03A)
3.2.2.5.22. VirtIO PCI Configuration Access Data Register (Address: 0x03B)
4.3.1. Avalon® Streaming Interface
4.3.2. Precision Time Measurement (PTM) Interface (Endpoint Only)
4.3.3. Interrupt Interface
4.3.4. Hard IP Reconfiguration Interface
4.3.5. Error Interface
4.3.6. Completion Timeout Interface
4.3.7. Configuration Intercept Interface
4.3.8. Power Management Interface
4.3.9. Hard IP Status Interface
4.3.10. Page Request Services (PRS) Interface (Endpoint Only)
4.3.11. Function-Level Reset (FLR) Interface (Endpoint Only)
4.3.12. SR-IOV VF Error Flag Interface (Endpoint Only)
4.3.13. General Purpose VSEC Interface
5.2.3.1. Device Capabilities
5.2.3.2. VirtIO Parameters
5.2.3.3. Link Capabilities
5.2.3.4. Legacy Interrupt Pin Register
5.2.3.5. MSI Capabilities
5.2.3.6. MSI-X Capabilities
5.2.3.7. Slot Capabilities
5.2.3.8. Latency Tolerance Reporting (LTR)
5.2.3.9. Process Address Space ID (PASID)
5.2.3.10. Device Serial Number Capability
5.2.3.11. Page Request Service (PRS)
5.2.3.12. Access Control Service (ACS)
5.2.3.13. Power Management
5.2.3.14. Vendor Specific Extended Capability (VSEC) Registers
5.2.3.15. TLP Processing Hints (TPH)
5.2.3.16. Address Translation Services (ATS) Capabilities
5.2.3.17. Precision Time Management (PTM)
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4.4.2. Command and Status Signals
Signal Name | Direction | Descriptions/Notes | Clock Domain |
---|---|---|---|
lnX_pipe_direct_rxstandby_i | Input | Synchronous rxstandby signal | pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_powerdown_i[1:0] | Input | PHY power state control signals | pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_rate_i[2:0] | Input | Gen1-5 rate change control signals: 000: Gen1 001: Gen2 010: Gen3 011: Gen4 100: Gen5 |
pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_txdetectrx_i | Input | Receiver detect control signal | pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_rxtermination_i | Input | Controls the presence of receiver terminations. This is a PIPE signal mainly intended for USB usage. Intel recommends driving this signal high (default).
|
pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_pclkchangeack_i | Input | Asserted by the MAC when a PCLK rate change or, if required, width change is complete and stable. | pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_tx_transfer_en_o | Output | This signal indicates when the EMIB is ready in PIPE mode. The soft IP controller must release the per-lane lnX_pipe_direct_pld_pcs_rst_n_i signal out of reset after the per-lane lnX_pipe_direct_tx_transfer_en_o signal is asserted. | pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_rxstandbystatus_o | Output | Indicates whether the PHY is active or in standby mode.
|
pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_pclkratechangeok_o | Output | This signal is asserted by the PHY when it is ready for the MAC to change the clock rate. |
pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_rxstatus_o | Output | Reflects the state of the high-speed receiver. A 1 on this bit indicates Rx is detected.
Note: The only status applicable to the PIPE SerDes architecture mode is "Receiver detected".
|
pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_phystatus_o | Output | Indicates the completion of several PHY functions including stable PCLK, after reset deassertion, power management state transitions, rate change and receiver detection. | pipe_direct_pld_tx_clk_out_o |
lnX_pipe_direct_cdrlockstatus_o | Output |
This is the Receiver CDR lock indicator.
If this signal is deasserted when it is expected to be asserted, it indicates a fault condition and the receiver should be reset. |
Async |
lnX_pipe_direct_cdrlock2data_o | Output |
This is the Receiver CDR data lock indicator.
Note: This signal will go low when the Soft IP Controller instructs the R-Tile Avalon Streaming IP to start an evaluation of the far end transmitter TX EQ settings (by setting the RxEqEval bit in the Rx Control 3 register). Once the evaluation is completed, the R-Tile Avalon Streaming IP will provide a Figure of Merit value and drive this signal high. For additional details on the Equalization sequence, refer to section 9.10 of the PIPE Specification 5.1.1.
|
Async |