All variants now support for Gen3 PIPE mode using the ModelSim® , NCSIM, and VCS simulators |
Better visibility for Gen3 simulations. |
All variants now support generation of predefined Signal Tap files for IP core debugging. |
Simplifies generation and configuration of Signal Tap files for debugging. |
For the Avalon® Memory-Mapped (Avalon-MM) with DMA variant, rearchitected Write DMA module for the 128-bit interface to the Application Layer. This version is final in the 16.0 release. |
Provides higher throughput for external memories. |
For the Avalon® -MM with DMA variant, the 256-bit interface to the Application Layer now supports a maximum transfer size of 64 kilobyte (KB). |
Large transfers require fewer descriptor table entries. |
For the Avalon Streaming (Avalon-ST) with Single Root I/O Virtualization (SR-IOV) variant, rearchitected the SR-IOV bridge to support 4 Physical Functions (PFs) and 2048 Virtual Functions (VFs). This new version is preliminary in the 16.0 release. |
Improves support for designs requiring more PFs and VFs. This new version is not backwards compatible with the previous 15.1 release. |
For the Avalon-ST with SR-IOV variant, added support for Address Translation Services (ATS) and TLP Processing Hints (TPH). |
Support for SR-IOV. |
For the Avalon-ST with SR-IOV variant, added Control Shadow interface to read the current settings for some of the VF Control Register fields in the PCI and PCI Express Configuration Spaces. |
Improves visibility for VFs. |
The Avalon-ST Streaming with SR-IOV variant now requires a license. |
You must purchase a license for this variant to run in hardware that is not connected to a host computer running the Quartus® Prime software. |