Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

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Date 12/14/2020
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1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes x
1.1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v20.4 1.2. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v18.0 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v17.1 1.4. Intel® Arria® 10 Hard IP for PCI Express* IP Core v17.0 1.5. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.1 1.6. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.0 1.7. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.1 1.8. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.0 1.9. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.1 1.10. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.0 Intel® Arria® 10 Edition 1.11. Intel® Arria® 10 Hard IP for PCI Express* IP Core v13.1 Arria 10 Edition
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v17.1

Table 3.  17.1 November 2017
Description Impact
Added support for Intel® Cyclone® 10 GX devices. Intel® Cyclone® 10 GX devices support a single Gen1 and Gen2 IP core at up to the Gen2 x4 data rate. You can use the lower cost Intel® Cyclone® 10 GX device to implement PCIe* for up to Gen2 x4 variants.
Added Enable RX-polarity inversion soft logic parameter to the PHY Characteristics tab of the component parameter editor.

This parameter mitigates a RX-polarity the following inversion problem. When the Intel® Cyclone® 10 GX or Intel® Arria® 10 Hard IP core receives TS2 training sequences during the Polling.Config state, when you have not enabled the automatic polarity inversion parameter, automatic lane polarity inversion is not guaranteed. The link may train to a smaller than expected link width or may not train successfully. This problem can affect configurations with any PCIe* speed and width. When you include this parameter, polarity inversion is available for all configurations except Gen1 x1. This fix does not support CvP or autonomous mode

Refer to the links below for additional information.

The Root Port is preliminary in the 17.1 release. You can enable the Root Port using the parameter editor. The Root Port supports basic simulation and compilation. However, the Root Port is not fully verified. You may find functional problems in the current release.
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