Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

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ID 683487
Date 12/14/2020
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1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes x
1.1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v20.4 1.2. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v18.0 1.3. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v17.1 1.4. Intel® Arria® 10 Hard IP for PCI Express* IP Core v17.0 1.5. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.1 1.6. Intel® Arria® 10 Hard IP for PCI Express* IP Core v16.0 1.7. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.1 1.8. Intel® Arria® 10 Hard IP for PCI Express* IP Core v15.0 1.9. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.1 1.10. Intel® Arria® 10 Hard IP for PCI Express* IP Core v14.0 Intel® Arria® 10 Edition 1.11. Intel® Arria® 10 Hard IP for PCI Express* IP Core v13.1 Arria 10 Edition
1. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core Release Notes

1.2. Intel® Arria® 10 and Intel® Cyclone® 10 GX Hard IP for PCI Express* IP Core v18.0

Table 2.  18.0 May 2018
Description Impact
Support for Root Port mode is preliminary in the 18.0 release. You can enable the Root Port mode using the parameter editor. The Root Port supports basic simulation and compilation. However, the Root Port is not fully verified. You may find functional problems in the current release.
msi_control[15:0] are not wired correctly in the generated IP. If you enable MSI/MSI-X functionality in the design, you need to connect this port to the top-level instantiation.
VHDL NCSim* simulation support. For Intel® Quartus® Prime Standard Edition, NCSim* VHDL simulation is not supported in the 18.0 release.
Level Two Title