Intel® Arria® 10 and Intel® Cyclone® 10 Avalon® Memory-mapped Interface for PCIe* Design Example User Guide

Download PDF
ID 683476
Date 1/13/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-mapped Hard IP for PCIe Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components for the Avalon® -MM Endpoint 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design in Hardware
2. Design Example Description x
2.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.2. Intel® Arria® 10 Development Kit Conduit Interface
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-mapped Hard IP for PCIe Design Example User Guide

1.3. Generating the Design

  1. Launch Platform Designer.
    • If you have an existing .qsys file in your directory, the Open System dialog box appears. Click New to specify a Quartus Prime project name and custom IP variation name for your design. Then, click Create.
    • If not, a new project is automatically created. Save it before moving to the next step.
  2. In the IP Catalog, locate and select Intel® Arria® 10/Cyclone 10 Hard IP for PCI Express. The parameter editor appears.
  3. On the IP Settings tabs, specify the parameters for your IP variation.
  4. In the Connections panel, make the following dummy connection: rxm_bar0 to txs slave interface.
    Platform Designer determines the size of the Avalon® -MM BAR master from its connection to an Avalon® -MM slave device. When you generate the example design, this connection is removed.
  5. Remove the clock_in and reset_in components that were instantiated by default.
  6. On the Example Design tab, the PIO design is available for your IP variation.
  7. For Example Design Files, select the Simulation and Synthesis options.
  8. For Generated HDL Format, only Verilog is available.
  9. For Target Development Kit, select the Intel® Arria® 10 GX FPGA Development Kit option. Currently, there is no option to select an Intel® Cyclone® 10 GX Development Kit when generating an example design.
  10. Click Generate Example Design. The software generates all files necessary to run simulations and hardware tests on the Intel® Arria® 10 FPGA Development Kit.
Level Two Title