Intel® Arria® 10 and Intel® Cyclone® 10 Avalon® Memory-mapped Interface for PCIe* Design Example User Guide

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ID 683476
Date 1/13/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-mapped Hard IP for PCIe Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components for the Avalon® -MM Endpoint 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design in Hardware
2. Design Example Description x
2.1. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.2. Intel® Arria® 10 Development Kit Conduit Interface
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® Memory-mapped Hard IP for PCIe Design Example User Guide

1.2. Design Components for the Avalon® -MM Endpoint

Figure 3. Block Diagram for the Platform Designer PIO Design Example Simulation Testbench
Level Two Title