Intel® Arria® 10 and Intel® Cyclone® 10 Avalon® Memory-mapped Interface for PCIe* Design Example User Guide
2.2. Intel® Arria® 10 Development Kit Conduit Interface
The Intel® Arria® 10 Development Kit conduit interface signals are optional signals that allow you to connect your design to the Intel® Arria® 10 FPGA Development Kit. Enable this interface by selecting Enable Intel® Arria® 10 FPGA Development Kit connection on the Configuration, Debug, and Extension Options tab of the component GUI. The devkit_status output port includes signals useful for debugging.
Signal Name | Direction | Description |
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devkit_status[255:0] | Output | The devkit_status[255:0] bus comprises the following status signals :
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devkit_ctrl[255:0] | Input | The devkit_ctrl[255:0] bus comprises the following status signals. You can optionally connect these pins to an on-board switch for PCI-SIG compliance testing, such as bypass compliance testing.
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