2.11.3. TX PCS Interface to User Logic

E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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2.11.3. TX PCS Interface to User Logic

The E-Tile Hard IP for Ethernet Intel FPGA IP TX client interface in PCS Only variations employs the Media Independent Interface (MII) protocol.

The client acts as a source and the TX PCS acts as a sink in the transmit direction.

Table 32. Signals of the MII TX Client InterfaceAll interface signals are clocked by the TX clock. The signal names are standard Avalon® streaming interface signals with slight differences to indicate the variations. For example:

For variants with single 10GE/25GE channel: `i_sl_tx_data`

For variants with more than 1 channel: `i_sl_tx_data[n-1:0]`

For variants with single 100GE channel: `i_tx_data`
Signal Name	Width	Description
`i_sl_clk_tx` `i_sl_clk_tx[n-1:0]` `i_clk_tx`	1 bit for each channel	The TX clock for the IP core that drives the channel.
`i_sl_tx_mii_d` `i_sl_tx_mii_d[n-1:0]` `i_tx_mii_d`	64 bits for each channel (10G/25G) 256 bits(100G)	TX MII data. Data must be in MII encoding. `i_tx_mii_d[7:0]` holds the first byte the IP core transmits on the Ethernet link. `i_tx_mii_d[0]` holds the first bit the IP core transmits on the Ethernet link. While the TX MII valid signal has the value of 0 or the alignment marker insertion bit signal has the value of 1, and for one additional clock cycle, you must hold the value of this signal stable. We refer to this behavior as freezing the signal value.
`i_sl_tx_mii_c` `i_sl_tx_mii_c[n-1:0]` `i_tx_mii_c`	8 bits for each channel (10G/25G) 32 bits (100G)	TX MII control bits. Each bit corresponds to a byte of the TX MII data signal. For example, `i_tx_mii_c[0]` corresponds to `i_tx_mii_d[7:0]`, `i_tx_mii_c[1]` corresponds to `i_tx_mii_d[15:8]`, and so on. If the value of a bit is 1, the corresponding data byte is a control byte. If the value of a bit is 0, the corresponding data byte is data. The Start of Packet byte (0xFB), End of Packet byte (0xFD), Idle bytes (0x07), and error byte (0xFE) are control bytes, but the preamble bytes, Start of Frame (SFD) byte (0xD5), CRC bytes, and payload bytes are data bytes. While the TX MII valid signal has the value of 0 or the alignment marker insertion bit signal has the value of 1, you must freeze the value of this signal.
`i_sl_tx_mii_valid` `i_sl_tx_mii_valid[n-1:0]` `i_tx_mii_valid`	1 bit for each channel	Indicates that the TX MII data signal is valid. You must assert this signal a fixed number of clock cycles after the IP core raises ready signal, and must deassert this signal the same number of clock cycles after the IP core deasserts the ready signal. The number must be in the range of 1–10 clock cycles. While you hold the value of this signal at 0, you must freeze the values of both TX MII data and TX MII control bits signals stable.
`o_sl_tx_mii_ready` `o_sl_tx_mii_ready[n-1:0]` `o_tx_mii_ready`	1 bit for each channel	Indicates the PCS is ready to receive new data.
`i_sl_tx_mii_am` `i_sl_tx_mii_am[n-1:0]` `i_tx_mii_am`	1 bit for each channel	Alignment marker insertion bit. In 100G variations, you must hold this signal asserted for 5 consecutive clock cycles. In 25Gx1 with RS-FEC variations, you must hold this signal asserted for 4 consecutive clock cycles. In 10Gx1 or 25Gx1 without RS-FEC variations, you must tie this signal low. The number of valid clock cycles from deassertion of the alignment marker insertion bit signal to reassertion of the alignment marker insertion bit signal is the `am_period`. For an example that handles this setting for simulation and drives the `i_tx_mii_am` signal appropriately for simulation, refer to the IP core design example for PCS Only variations. For information about how to generate the IP core design example, refer to the Design Example User Guide. For information about the `sim_mode` RTL parameter, refer to the RTL Parameters section of this user guide. While you hold the value of this signal at 1, you must freeze the values of both TX MII data and TX MII control bits signals.

Figure 42. Transmitting Data Using the PCS Mode TX Interface

The figure above shows how to write packets directly to the PCS mode TX interface.

The packets are written using MII.
- Each byte in i_tx_mii_d has a corresponding bit in i_tx_mii_c that indicates whether the byte is a control byte or a data byte; for example, i_tx_mii_c[1] is the control bit for i_tx_mii_d[15:8].
i_tx_mii_valid should conform to these conditions:
- Assert the valid signal only when the ready signal is asserted, and deassert only when the ready signal is deasserted.
- The two signals can be spaced by a fixed latency between 1 and 10 cycles.
- When the valid signal deasserts, i_tx_mii_d and i_tx_mii_c must be paused.
The byte order for the PCS mode TX interface is opposite of the byte order for the MAC client. Bytes flow from right to left; the first byte to be transmitted from the interface is i_tx_mii_d[7:0].
The bit order for the PCS mode TX interface is the same as the bit order of the MAC client. The first bit to be transmitted from the interface is i_tx_mii_d[0].

Note: The PCS mode TX interface is not SOP aligned. Any legal ordering of packets in MII format is accepted.

Table 33. Writing a Start Packet Block with Preamble to the PCS Mode TX Interface
MII Data		MII Control		Ethernet Packet Byte
i_tx_mii_d[7:0]	0xFB	i_tx_mii_c[0]	1	Start of Packet
i_tx_mii_d[15:8]	0x55	i_tx_mii_c[1]	0	Preamble
i_tx_mii_d[23:16]	0x55	i_tx_mii_c[2]	0	Preamble
i_tx_mii_d[31:24]	0x55	i_tx_mii_c[3]	0	Preamble
i_tx_mii_d[39:32]	0x55	i_tx_mii_c[4]	0	Preamble
i_tx_mii_d[47:40]	0x55	i_tx_mii_c[5]	0	Preamble
i_tx_mii_d[55:48]	0x55	i_tx_mii_c[6]	0	Preamble
i_tx_mii_d[63:56]	0xD5	i_tx_mii_c[7]	0	SFD

Figure 43. Inserting Alignment Markers

The timing of alignment marker insertion is very rigid. Alignment markers cannot be delayed without disrupting the Ethernet link. Use valid cycles to count the alignment markers. When i_tx_mii_valid is low, the alignment marker counters and input must freeze.

The number of cycles for i_tx_mii_am to remain high depends on the rate of the interface:

100G: 5 cycles
25Gx1 with RS-FEC: 4 cycles
10Gx1 or 25x1 without PTP or RS-FEC: 0 cycle (tie low)

The number of cycles for am period depends on the rate of the interface and whether in simulation or hardware:

In simulation, it is common to use a reduced am period for both sides of the link to increase lock-time speed.
- 100G link: 315
- 25Gx1 link with RS-FEC: 5119
In hardware.
- 100G link: 81915
- 25Gx1 link with RS-FEC: 81916

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E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

2.11.3. TX PCS Interface to User Logic