E-tile Hard IP User Guide: E-Tile Hard IP for Ethernet and E-Tile CPRI PHY Intel® FPGA IPs

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Date 8/04/2021
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Document Table of Contents
Document Table of Contents x
1. About E-tile Hard IP User Guide 2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core 3. About the E-Tile CPRI PHY Intel® FPGA IP 4. Supported Tools 5. E-tile Hard IP User Guide Archives
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core x
2.1. E-Tile Hard IP for Ethernet Intel FPGA IP Supported Features 2.2. E-Tile Hard IP for Ethernet Intel FPGA IP Overview 2.3. IP Core Device Family and Speed Grade Support 2.4. IP Core Verification 2.5. Resource Utilization 2.6. Release Information 2.7. Getting Started 2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters 2.9. Functional Description 2.10. Reset 2.11. Interfaces and Signals 2.12. Register Descriptions 2.13. Document Revision History for the E-tile Hard IP for Ethernet Intel FPGA IP Core
2.3. IP Core Device Family and Speed Grade Support x
2.3.1. E-Tile Hard IP for Ethernet Intel FPGA IP Device Family Support 2.3.2. E-Tile Hard IP for Ethernet Intel FPGA IP Device Speed Grade Support
2.4. IP Core Verification x
2.4.1. Simulation Environment 2.4.2. Compilation Checking 2.4.3. Hardware Testing
2.7. Getting Started x
2.7.1. Installing and Licensing Intel® FPGA IP Cores 2.7.2. Specifying the IP Core Parameters and Options 2.7.3. Generated File Structure 2.7.4. Integrating Your IP Core in Your Design 2.7.5. IP Core Testbenches 2.7.6. Compiling the Full Design
2.7.1. Installing and Licensing Intel® FPGA IP Cores x
2.7.1.1. Intel® FPGA IP Evaluation Mode
2.7.4. Integrating Your IP Core in Your Design x
2.7.4.1. Channel Placement 2.7.4.2. Pin Assignments 2.7.4.3. Clock Requirements 2.7.4.4. External Time-of-Day Module for Variations with 1588 PTP Feature 2.7.4.5. SDC for Multiple E-Tile Instances
2.7.4.1. Channel Placement x
2.7.4.1.1. Guidelines and Restrictions for 24-bonded Channels Variant 2.7.4.1.2. Guidelines and Restrictions for 16-bonded Channels Variant
2.8. E-Tile Hard IP for Ethernet Intel FPGA IP Parameters x
2.8.1. Parameter Editor Parameters 2.8.2. RTL Parameters
2.9. Functional Description x
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC 2.9.2. 1588 Precision Time Protocol Interfaces 2.9.3. PCS, OTN, FlexE, and Custom PCS Modes 2.9.4. Auto-Negotiation and Link Training 2.9.5. TX and RX RS-FEC 2.9.6. PMA Direct Mode 2.9.7. Dynamic Reconfiguration 2.9.8. Ethernet Adaptation Flow for 10G/25G and 100G/4x25G Dynamic Reconfiguration Design Example 2.9.9. Ethernet Adaptation Flow with PTP or with External AIB Clocking 2.9.10. Ethernet Adaptation Flow with Non-external AIB Clocking
2.9.1. E-Tile Hard IP for Ethernet Intel FPGA IP MAC x
2.9.1.1. MAC TX Datapath 2.9.1.2. MAC RX Datapath 2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) 2.9.1.4. Pause Control and Generation Interface 2.9.1.5. Pause Control Frame Filtering 2.9.1.6. Link Fault Signaling 2.9.1.7. Order of Ethernet Transmission
2.9.1.1. MAC TX Datapath x
2.9.1.1.1. TX Preamble, Start, and SFD Insertion 2.9.1.1.2. Source Address Insertion 2.9.1.1.3. Length/Type Field Processing 2.9.1.1.4. Frame Padding 2.9.1.1.5. Frame Check Sequence (CRC-32) Insertion 2.9.1.1.6. Inter-Packet Gap Generation and Insertion
2.9.1.2. MAC RX Datapath x
2.9.1.2.1. RX Preamble Processing 2.9.1.2.2. RX Strict SFD Checking 2.9.1.2.3. RX FCS Checking 2.9.1.2.4. RX Malformed Packet Handling 2.9.1.2.5. Removing PAD Bytes and FCS Bytes from RX Frames 2.9.1.2.6. RX Undersized Frames, Oversized Frames, and Frames with Length Errors 2.9.1.2.7. Inter-Packet Gap
2.9.1.3. Congestion and Flow Control Using PAUSE or Priority Flow Control (PFC) x
2.9.1.3.1. Conditions Triggering XOFF Frame Transmission 2.9.1.3.2. Conditions Triggering XON Frame Transmission
2.9.1.6. Link Fault Signaling x
2.9.1.6.1. Determining Link Fault Condition
2.9.2. 1588 Precision Time Protocol Interfaces x
2.9.2.1. Implementing a 1588 System That Includes a E-Tile Hard IP for Ethernet Intel FPGA IP 2.9.2.2. PTP Timestamp Accuracy 2.9.2.3. PTP Transmit Functionality 2.9.2.4. PTP Receive Functionality 2.9.2.5. External Time-of-Day Module for 1588 PTP Variations 2.9.2.6. PTP Timestamp and TOD Formats 2.9.2.7. 10G/25G TX and RX Unit Interval Adjustment 2.9.2.8. 10G/25G TX and RX PTP Extra Latency 2.9.2.9. 100G PTP TX User Flow 2.9.2.10. 100G PTP RX User Flow 2.9.2.11. 100G RX Virtual Lane Offset Calculation for No FEC Variants 2.9.2.12. 100G UI Adjustment 2.9.2.13. Minimum and Maximum Reference Time (TAM) Interval for UI Measurement (Hardware) 2.9.2.14. PTP System Considerations 2.9.2.15. Logic Lock Regions Requirements for PTP Accuracy Advanced Mode
2.9.3. PCS, OTN, FlexE, and Custom PCS Modes x
2.9.3.1. PCS Only Mode 2.9.3.2. OTN Mode 2.9.3.3. FlexE Mode 2.9.3.4. Custom PCS Mode
2.10. Reset x
2.10.1. Reset Sequence
2.10.1. Reset Sequence x
2.10.1.1. Reset Sequence with External AIB Clocking
2.11. Interfaces and Signals x
2.11.1. TX MAC Interface to User Logic 2.11.2. RX MAC Interface to User Logic 2.11.3. TX PCS Interface to User Logic 2.11.4. RX PCS Interface to User Logic 2.11.5. FlexE and OTN Mode TX Interface 2.11.6. FlexE and OTN Mode RX Interface 2.11.7. TX Custom PCS Interface to User Logic 2.11.8. RX Custom PCS Interface to User Logic 2.11.9. PMA Direct Interface 2.11.10. Custom Rate Interface 2.11.11. Deterministic Latency Interface 2.11.12. 1588 PTP Interface 2.11.13. Ethernet Link and Transceiver Signals 2.11.14. Reconfiguration Interfaces and Signals 2.11.15. Miscellaneous Status and Debug Signals 2.11.16. Reset Signals 2.11.17. Clocks
2.11.14. Reconfiguration Interfaces and Signals x
2.11.14.1. Ethernet Reconfiguration Interfaces 2.11.14.2. Transceiver Reconfiguration Interfaces 2.11.14.3. RS-FEC Reconfiguration Interfaces 2.11.14.4. PTP Reconfiguration Interfaces
2.11.17. Clocks x
2.11.17.1. Asynchronous Adapter Clock in 10G/25G Mode 2.11.17.2. Asynchronous Adapter Clock in 100G Mode 2.11.17.3. Clock Network Use Cases
2.11.17.3. Clock Network Use Cases x
2.11.17.3.1. Single 25G Ethernet Channel (with FEC) 2.11.17.3.2. Single 10G Ethernet Channel (without FEC) 2.11.17.3.3. Four 25G Ethernet Channels (with FEC) within a Single FEC Block 2.11.17.3.4. Ethernet 25G x 4 (FEC Off) 2.11.17.3.5. 10G/25G Ethernet Channel with Basic PTP Accuracy Mode 2.11.17.3.6. 10G/25G Ethernet Channel with Advanced PTP Accuracy Mode 2.11.17.3.7. 100G Ethernet with Aggregated FEC 2.11.17.3.8. 100G Ethernet with PTP 2.11.17.3.9. Single 25G Synchronous Ethernet Channel 2.11.17.3.10. Multiple 25G Synchronous Ethernet Channels
2.12. Register Descriptions x
2.12.1. Auto Negotiation and Link Training Registers 2.12.2. PHY Registers 2.12.3. TX MAC Registers 2.12.4. RX MAC Registers 2.12.5. Pause and Priority- Based Flow Control Registers 2.12.6. TX Statistics Counter Registers 2.12.7. RX Statistics Counter Registers 2.12.8. 1588 PTP Registers 2.12.9. RS-FEC Registers 2.12.10. PMA Registers
2.12.1. Auto Negotiation and Link Training Registers x
2.12.1.1. ANLT Sequencer Config 2.12.1.2. ANLT Sequencer Status 2.12.1.3. Auto Negotiation Config Register 1 2.12.1.4. Auto Negotiation Config Register 2 2.12.1.5. Auto Negotiation Status Register 2.12.1.6. Auto Negotiation Config Register 3 2.12.1.7. Auto Negotiation Config Register 4 2.12.1.8. Auto Negotiation Config Register 5 2.12.1.9. Auto Negotiation Config Register 6 2.12.1.10. Auto Negotiation Status Register 1 2.12.1.11. Auto Negotiation Status Register 2 2.12.1.12. Auto Negotiation Status Register 3 2.12.1.13. Auto Negotiation Status Register 4 2.12.1.14. Auto Negotiation Status Register 5 2.12.1.15. AN Channel Override 2.12.1.16. Consortium Next Page Override 2.12.1.17. Consortium Next Page Link Partner Status 2.12.1.18. Link Training Config Register 1 2.12.1.19. Link Training Status Register 1 2.12.1.20. Link Training Config Register for Lane 0 2.12.1.21. Link Training Config Register for Lane 1 2.12.1.22. Link Training Config Register for Lane 2 2.12.1.23. Link Training Config Register for Lane 3
2.12.2. PHY Registers x
2.12.2.1. PHY Module Revision ID 2.12.2.2. PHY Scratch Register 2.12.2.3. Loopback Mode 2.12.2.4. PHY Configuration 2.12.2.5. Reset Sequencer RS-FEC Disable 2.12.2.6. RX CDR PLL Locked 2.12.2.7. TX Datapath Ready 2.12.2.8. Frame Errors Detected 2.12.2.9. Clear Frame Errors 2.12.2.10. RX PCS Status for AN/LT 2.12.2.11. PCS Error Injection 2.12.2.12. Alignment Marker Lock 2.12.2.13. Change in RX PCS Deskew Status 2.12.2.14. BER Count 2.12.2.15. Transfer Ready (AIB reset) Status for EHIP, ELANE, and PTP Channels 2.12.2.16. EHIP, ELANE, and RS-FEC Reset Status 2.12.2.17. PCS Virtual Lane 0 2.12.2.18. PCS Virtual Lane 1 2.12.2.19. PCS Virtual Lane 2 2.12.2.20. PCS Virtual Lane 3 2.12.2.21. Recovered Clock Frequency in KHz 2.12.2.22. TX Clock Frequency in KHz 2.12.2.23. Configuration Fields for TX PLD 2.12.2.24. Status for TX PLDs 2.12.2.25. Status for Dynamic Deskew Buffer 2.12.2.26. Configuration for RX PLD Block 2.12.2.27. Configuration for RX PCS 2.12.2.28. BIP Counter 0 2.12.2.29. BIP Counter 1 2.12.2.30. BIP Counter 2 2.12.2.31. BIP Counter 3 2.12.2.32. BIP Counter 4 2.12.2.33. BIP Counter 5 2.12.2.34. BIP Counter 6 2.12.2.35. BIP Counter 7 2.12.2.36. BIP Counter 8 2.12.2.37. BIP Counter 9 2.12.2.38. BIP Counter 10 2.12.2.39. BIP Counter 11 2.12.2.40. BIP Counter 12 2.12.2.41. BIP Counter 13 2.12.2.42. BIP Counter 14 2.12.2.43. BIP Counter 15 2.12.2.44. BIP Counter 16 2.12.2.45. BIP Counter 17 2.12.2.46. BIP Counter 18 2.12.2.47. BIP Counter 19 2.12.2.48. Timer Window for Hi-BER Checks 2.12.2.49. Hi-BER Frame Errors 2.12.2.50. Error Block Count 2.12.2.51. Deskew Depth 0 2.12.2.52. Deskew Depth 1 2.12.2.53. Deskew Depth 2 2.12.2.54. Deskew Depth 3 2.12.2.55. RX PCS Test Error Count
2.12.3. TX MAC Registers x
2.12.3.1. TX MAC Module Revision ID 2.12.3.2. TX MAC Scratch Register 2.12.3.3. Link Fault Configuration 2.12.3.4. IPG Words to remove per Alignment Marker Period 2.12.3.5. Maximum TX Frame Size 2.12.3.6. TX MAC Configuration 2.12.3.7. EHIP TX MAC Feature Configuration 2.12.3.8. TX MAC Source Address Lower Bytes 2.12.3.9. TX MAC Source Address Higher Bytes
2.12.4. RX MAC Registers x
2.12.4.1. RX MAC Module Revision ID 2.12.4.2. RX MAC Scratch Register 2.12.4.3. Maximum RX Frame Size 2.12.4.4. RX CRC Forwarding 2.12.4.5. Link Fault Status 2.12.4.6. RX MAC Configuration 2.12.4.7. EHIP RX MAC Feature Configuration
2.12.5. Pause and Priority- Based Flow Control Registers x
2.12.5.1. TXSFC Module Revision ID 2.12.5.2. TX SFC Scratch Register 2.12.5.3. Enable TX Pause Ports 2.12.5.4. TX Pause Request 2.12.5.5. Enable Automatic TX Pause Retransmission 2.12.5.6. Retransmit Holdoff Quanta 2.12.5.7. Retransmit Pause Quanta 2.12.5.8. Enable TX XOFF 2.12.5.9. Enable Uniform Holdoff 2.12.5.10. Set Uniform Holdoff 2.12.5.11. Lower 4 bytes of the Destination address for Flow Control 2.12.5.12. Higher 2 bytes of the Destination address for Flow Control 2.12.5.13. Lower 4 bytes of the Source address for Flow Control frames 2.12.5.14. Higher 2 bytes of the Source address for Flow Control frames 2.12.5.15. TX Flow Control Feature Configuration 2.12.5.16. Pause Quanta 0 2.12.5.17. Pause Quanta 1 2.12.5.18. Pause Quanta 2 2.12.5.19. Pause Quanta 3 2.12.5.20. Pause Quanta 4 2.12.5.21. Pause Quanta 5 2.12.5.22. Pause Quanta 6 2.12.5.23. Pause Quanta 7 2.12.5.24. PFC Holdoff Quanta 0 2.12.5.25. PFC Holdoff Quanta 1 2.12.5.26. PFC Holdoff Quanta 2 2.12.5.27. PFC Holdoff Quanta 3 2.12.5.28. PFC Holdoff Quanta 4 2.12.5.29. PFC Holdoff Quanta 5 2.12.5.30. PFC Holdoff Quanta 6 2.12.5.31. PFC Holdoff Quanta 7 2.12.5.32. RXSFC Module Revision ID 2.12.5.33. RXSFC Scratch Register 2.12.5.34. Enable RX Pause Frame Processing 2.12.5.35. Forward Flow Control Frames 2.12.5.36. Lower 4 bytes of the Destination address for RX Pause Frames 2.12.5.37. Higher 2 bytes of the Destination address for RX Pause Frames 2.12.5.38. RX Flow Control Feature Configuration
2.12.6. TX Statistics Counter Registers x
2.12.6.1. TX Statistics Registers
2.12.7. RX Statistics Counter Registers x
2.12.7.1. RX Statistics Registers
3. About the E-Tile CPRI PHY Intel® FPGA IP x
3.1. Supported Features 3.2. E-Tile CPRI PHY Intel® FPGA IP Overview 3.3. E-Tile CPRI PHY Device Family Support 3.4. Resource Utilization 3.5. Release Information 3.6. E-Tile CPRI PHY Intel FPGA IP Core Device Speed Grade Support 3.7. Getting Started 3.8. Parameter Settings 3.9. Functional Description 3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals 3.11. Registers 3.12. Document Revision History for the E-tile CPRI PHY Intel FPGA IP
3.7. Getting Started x
3.7.1. Installing and Licensing Intel® FPGA IP Cores 3.7.2. Specifying the IP Core Parameters and Options 3.7.3. Generated File Structure 3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement 3.7.5. IP Core Testbenches 3.7.6. Compiling the Full Design
3.7.1. Installing and Licensing Intel® FPGA IP Cores x
3.7.1.1. Intel® FPGA IP Evaluation Mode
3.7.4. E-Tile CPRI PHY Intel FPGA IP Channel Placement x
3.7.4.1. One 24.33024 Gbps channel with RS-FEC 3.7.4.2. Two 24.33024 Gbps Channel with RS-FEC 3.7.4.3. Three 24.33024 Gbps channels with RS-FEC 3.7.4.4. Four 24.33024 Gbps channels with RS-FEC 3.7.4.5. Restrictions
3.9. Functional Description x
3.9.1. CPRI PHY Functional Blocks 3.9.2. Dynamic Reconfiguration
3.9.1. CPRI PHY Functional Blocks x
3.9.1.1. E-tile Native PHY 3.9.1.2. Soft Reset Sequencer 3.9.1.3. Latency Measurement
3.9.1.3. Latency Measurement x
3.9.1.3.1. Deterministic Latency Calculation
3.10. E-Tile CPRI PHY Intel FPGA IP Interface Signals x
3.10.1. Clock Signals 3.10.2. TX MII Interface 3.10.3. RX MII Interface 3.10.4. TX 8B/10B Interface 3.10.5. RX 8B/10B Interface 3.10.6. Status Interface for 64B/66B Line Rate 3.10.7. Status Interface for 8B/10B Line Rate 3.10.8. Serial I/O Pins 3.10.9. Reconfiguration Interfaces (Avalon-MM)
3.10.9. Reconfiguration Interfaces (Avalon-MM) x
3.10.9.1. CPRI PHY Reconfiguration Interface 3.10.9.2. Transceiver Reconfiguration Interface 3.10.9.3. RS-FEC Reconfiguration Interface
3.11. Registers x
3.11.1. PHY Registers 3.11.2. CPRI PHY Registers 3.11.3. PMA Registers 3.11.4. RS-FEC Registers
3.11.3. PMA Registers x
3.11.3.1. Minimizing PMA Adaptation Time
4. Supported Tools x
4.1. E-Tile Channel Placement Tool 4.2. Ethernet Toolkit Overview 4.3. Document Revision History for the E-tile Channel Placement Tool and the Ethernet Link Inspector
4.2. Ethernet Toolkit Overview x
4.2.1. Features
1. About E-tile Hard IP User Guide
2. About the E-Tile Hard IP for Ethernet Intel FPGA IP Core
3. About the E-Tile CPRI PHY Intel® FPGA IP
4. Supported Tools
5. E-tile Hard IP User Guide Archives

2.11.12. 1588 PTP Interface

The E-Tile Hard IP for Ethernet Intel FPGA IP 1588 PTP Interface is available for 10G/25G designs when you turn on Enable IEEE 1588 PTP for 10G/25G channels in 100GE or 1 to 4 10GE/25GE with optional RS-FEC and 1588 PTP variation. The 1588 Precision Time Protocol (PTP) timestamp information provided is as defined in the IEEE 1588-2008 Precision Clock Synchronization Protocol for Networked Measurement and Control Systems Standard.

These signals are active only when your selected channel is configured to provide a MAC+PTP+PCS stack.

All 1-step and 2-step TX/RX Timestamp interface signals are common for both, basic and advanced PTP accuracy modes with the exception of these TOD interface signals:
  • In basic PTP accuracy mode: i_ptp_tod
  • In advanced PTP accuracy mode: i_sl_ptp_tx_tod/i_sl_ptp_tx_tod
All interface signals, except the TOD interface signals29 and PTP ready signals30, are clocked by the TX or RX clock.
  • TX clock represents i_sl_clk_tx clock when the asynchronous adapter is disabled and i_sl_async_clk_tx clock when the asynchronous adapter is enabled.
  • RX clock represents i_sl_clk_rx clock when the asynchronous adapter is disabled and i_sl_async_clk_rx clock when the asynchronous adapter is enabled.
The signal names are standard Avalon® streaming interface signals with slight differences to indicate the variations. For example:
  • For 100GE channel or single channel 10GE/25GE: i_ptp_ins_ets
  • For selected 10GE/25GE channel: i_sl_ptp_ins_ets[(n*width)-1:0]
Table 46.  Signals of the 1-Step TX Timestamp Interface

Signal Name

Width

Description

i_ptp_ins_ets

i_sl_ptp_ins_ets[n-1:0]

1

Egress timestamp into the current TX Packet on the respective channel.

  • Valid only when the TX valid and TX SOP signals are asserted.
  • Do not use when the TX skip CRC signal (e.g. i_tx_skip_crc) is asserted. The CRC for the TX packet must be recalculated after the egress timestamp is written.
  • Do not use when the residence time timestamp signal (e.g. i_ptp_ins_cf) is asserted. You cannot update residence time and insert an egress timestamp on the same packet.
  • Set the position of the PTP timestamp field in the TX packet (e.g. i_ptp_ts_offset) to the byte position of the start of the timestamp field in the PTP header.
  • Set the format for the PTP 1-step operation (e.g. i_ptp_ts_format) to the desired timestamp format.
  • If the selected timestamp format requires a 96b timestamp, set the PTP correction field in the TX packet (e.g. i_ptp_cf_offset) to the byte position of the start of the correction field in the PTP header.

i_ptp_ins_cf

i_sl_ptp_ins_cf[n-1:0]

1

Residence time timestamp into the correction field in the current TX packet on the respective channel.

  • Valid only when the TX valid and TX SOP signals are asserted.
  • Do not use when the TX skip CRC signal (e.g. i_tx_skip_crc) is asserted. The CRC for the TX packet must be recalculated after the residence time is written.
  • Do not use when the egress time timestamp signal (e.g. i_ptp_ins_ets) is asserted. You cannot update residence time and insert an egress timestamp on the same packet.
  • Provide the core with the ingress timestamp of the current packet (e.g. assert i_ptp_tx_its) when it entered the system, so that a residence time can be calculated.
  • Set the position of the PTP correction field in the TX packet (e.g. i_ptp_cf_offset) to the byte position of the start of the correction field in the PTP header.
    Note: If the PTP packet resides in the system for more than 4 seconds, the correction field will show a mismatched value with a very large number.
  • Set i_ptp_ts_format to 0.

i_ptp_zero_csum

i_sl_ptp_zero_csum[n-1:0]

1

Overwrites the checksum in a UDP packet carried inside the current TX packet with zeros.

  • Valid only when the TX valid and TX SOP signals are asserted.
  • Do not use when the TX skip CRC signal (e.g. i_tx_skip_crc) is asserted. The CRC for the TX packet must be recalculated after the checksum is changed.
  • Do not use when the update extended bytes field signal (e.g i_ptp_update_eb) is asserted. You cannot set a UDP checksum to 0, and update an extension field to cancel out checksum changes on the same packet.
  • Set the position of the UDP checksum field in the TX packet (e.g. i_ptp_csum_offset) to the byte position of the start of the UDP checksum in the TX packet.

i_ptp_update_eb

i_sl_ptp_update_eb[n-1:0]

1

Overwrites the extended bytes field in an IPv6 packet carried inside the current TX packet with a value that cancels out changes to the checksum due to changes to the UDP packet.

  • Valid only when the TX valid and TX SOP signals are asserted.
  • Do not use when the TX skip CRC signal (e.g. i_tx_skip_crc) is asserted. The CRC for the TX packet must be recalculated after the checksum is changed.
  • Do not use when the overwrite a UDP checksum with zeros signal (e.g. i_ptp_zero_csum) is asserted. You cannot set a UDP checksum to 0, and update an extension field to cancel out checksum changes on the same packet.
  • Set the position of the first byte of the extended bytes field in the TX packet (e.g. i_ptp_eb_offset) to the byte position of the start of the UDP checksum in the TX packet.

i_ptp_ts_format

i_sl_ptp_ts_format[n-1:0]

1

Format of the PTP 1-step operation on the respective channel.

  • 0: Use IEEE 1588v2 timestamp and correction field formats (96 bits)
  • 1: Use IEEE 1588v1 timestamp format (64 bits)

Valid only when either the egress time timestamp signal (i_ptp_ins_ets) or the residence time timestamp signal ( i_ptp_ins_cf), and the TX valid signal, and SOP signal are asserted.

When i_ptp_ins_cf is asserted, this port must be set to 0. The correction field is only applicable to IEEE 1588v2 format.

i_ptp_ts_offset

i_sl_ptp_ts_offset[(n*16)-1:0]

16

Position of the PTP timestamp field in the current TX packet.

  • Valid only when the TX valid and TX SOP signals are asserted.
  • It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0.
  • The IEEE 1588v2 PTP timestamp field is 10 octets long (80 bits), and the IEEE 1588v1 timestamp is 8 octets long (64bits), starting from the position given by the offset. Because the IEEE 1588v2 timestamps are actually 96 bits long, the lower 16 bits of the timestamp are placed in the lower 2 octets of the correction field.
CAUTION:
You must set the offset to a position within the TX packet, or the PTP insertion operation will fail. You must not also overlap the PTP fields.

i_ptp_cf_offset

i_sl_ptp_cf_offset[(n*16)-1:0]

16

Position of the PTP correction field in the current TX packet.

  • Valid only when the TX valid and TX SOP signals are asserted.
  • It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0.
  • The PTP correction field is 8 octets long, starting from the position given by the offset. When 96-bit timestamps are used, the MAC places the lower 16 bits of the timestamp in the lower 2 octets of the correction field.
CAUTION:
You must set the offset to a position within the TX packet, or the PTP insertion operation will fail. You must not also overlap the PTP fields.

i_ptp_csum_offset

i_sl_ptp_csum_offset[(n*16)-1:0]

16

Position of the first byte of a UDP checksum field in the current TX packet.

  • Valid only when the checksum overwrite in a UDP packet (e.g. i_ptp_zero_csum), TX valid, TX SOP signals are asserted.
  • It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0.
CAUTION:
You must set the offset to a position within the TX packet, or the PTP insertion operation will fail. You must not also overlap the PTP fields.

i_ptp_eb_offset

i_sl_ptp_eb_offset[(n*16)-1:0]

16

Position of the first byte of extended bytes field in the current TX packet.

  • Valid only when the extended bytes overwrite in an IPv6 packet (e.g. i_ptp_update_eb), TX valid, TX SOP signals are asserted.
  • It is the offset of the first octet of the field from the start of the frame, where the first byte of the frame (the first destination MAC address octet) is position 0.
CAUTION:
You must set the offset to a position within the TX packet, or the PTP insertion operation will fail. You must not also overlap the PTP fields.

i_ptp_tx_its

i_sl_ptp_tx_its[(n*96)-1:0]

96

Ingress timestamp for a TX packet that requires a residence time calculation (e.g. i_ptp_ins_cf = 1).

This timestamp is the time at which the packet arrives in the system. The TX MAC compares this time to the time at which the packet leaves the system to generate a residence time. You must set the i_ptp_ts_format to 0. Residence time calculation/correction is only applicable to IEEE 1588v2 format.

Valid only when the TX valid and TX SOP signals are asserted.

Table 47.  Signals of the 2-Step TX Timestamp InterfaceUse the 2-step TX Timestamp to request for 2-step TX Timestamps when a packet is transmitted.

Signal Name

Width

Description

i_ptp_ts_req

i_sl_ptp_ts_req[n-1:0]

1

Request a 2-step timestamp signal for the current TX packet.

When asserted, generates a TX timestamp for the current packet.

Valid only when the TX valid and TX SOP signals are asserted.

i_ptp_fp

i_sl_ptp_fp[(n*8)-1:0]

8

Fingerprint signal for current TX packet.

Assigns an 8-bit fingerprint to a TX packet that is being transmitted, so that the 2-step or 1-step PTP timestamp associated with the TX packet can be identified. The timestamp returns with the same fingerprint.
  • Use a range of fingerprints from 0..31 or larger, to avoid the possibility of assigning the same fingerprint to 2 TX packets that are being processed.
  • Choose an easy-to-decode null fingerprint for any packets that do not require an egress timestamp. For example, if you use a range of 0..31, make 32 the null fingerprint.

Valid only when the TX valid and TX SOP signals are asserted.

o_ptp_ets_valid

o_sl_ptp_ets_valid[n-1:0]

1

1-step or 2-step egress timestamp valid signal.

When asserted, the fingerprint and egress timestamp signals present valid output on this cycle.

This signal is asserted after the timestamp is generated in one of these scenarios:
  • You assert i_ptp_ts_req to request 2-step timestamp.
  • You assert i_ptp_ins_ets to request 1-step timestamp insertion.

o_ptp_ets

o_sl_ptp_ets[(n*96)-1:0]

96

2-step or 1-step egress timestamp signal.

This port presents an egress timestamp for the TX Packet that was transmitted with the fingerprint given by o_ptp_ets_fp.

Following conditions apply to this signal:

  • Valid only when the egress timestamp valid (o_ptp_ets_valid) signal is asserted.
  • The timestamp is in 1588v2 format (96b).
  • This corresponds to the generated timestamp when you assert i_ptp_ts_req to request 2-step timestamp or when you assert i_ptpt_ins_ets to request 1-step timestamp insertion.
  • The timestamp is for the packet whose fingerprint matches the fingerprint with the egress timestamp.
  • All timestamps are referenced to the copy of the Time-of-Day provided to the IP core through the i_ptp_tod port.

o_ptp_ets_fp

o_sl_ptp_ets_fp[(n*8)-1:0]

8

Fingerprint for the current 2-step or 1-step egress timestamp. You can use the fingerprint to determine which TX packet the timestamp belongs to.

Valid only when the egress timestamp valid signal ( o_ptp_ets_valid) is asserted.

Table 48.  Signals of the Time of Day InterfaceThe time of day interface allows the core to reference all of its timestamps to the time of day as it is known locally.

Signal Name

Width

Description

i_ptp_tod

96

When you set the PTP Accuracy Mode to Basic Mode, this signal presents the current Time of Day, according to the local clock, to the Ethernet IP core.

All channels in the same IP core share the same ToD port. When your design implements multiple IP cores, each IP core requires a ToD IP.

The timestamp is in IEEE 1588v2 format (96b).

i_sl_ptp_tx_tod[(n*96)-1:0]

96

When you set the PTP Accuracy Mode to Advanced Mode, represents the TX Time of Day, according to the local clock.

The timestamp is in IEEE 1588v2 format (96 bits).

i_sl_ptp_rx_tod[(n*96-1):0]

96

When you set the PTP Accuracy Mode to Advanced Mode, represents the RX Time of Day, according to the local clock.

The timestamp format is in IEEE 1588v2 format (96 bits).

Table 49.  Signals of the RX Timestamp InterfaceThe RX Timestamp interface allows each channel to provide RX timestamps when packets arrive.

Signal Name

Width

Description

o_ptp_rx_its

o_sl_ptp_rx_its[(n*96)-1:0]

96

Ingress RX timestamp signal.

Presents the ingress timestamp for the incoming RX packet on the respective channel.

Valid only when the RX valid and RX SOP signals are asserted.

The timestamp is in 1588v2 format (96b).
Table 50.  Signals of the PTP Status InterfaceThe PTP Status interface lets applications using PTP functions know when the PTP timestamp logic is ready for use.

Signal Name

Width

Description

o_tx_ptp_ready

o_sl_tx_ptp_ready[n-1:0]

1

TX PTP ready signal.

When asserted, the core to ready to request for TX PTP functions on the respective channel.

o_rx_ptp_ready

o_sl_rx_ptp_ready[n-1:0]

1

RX PTP ready signal.

When asserted,the RX PTP logic ready for use on the respective channel. After reset and PMA adaptation, the signal gets asserted after link partner sends up to 20 Ethernet packets.

29 The applicable TOD interface signals: i_ptp_tod in the basic PTP accuracy mode, i_sl_ptp_tx_tod/i_sl_ptp_rx_tod in the advance PTP accuracy mode.
30 The applicable PTP ready signals: o_tx_ptp_ready/o_sl_tx_ptp_ready and o_rx_ptp_ready/o_sl_rx_ptp_ready.
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