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3.1. Creating a New FPGA Design Project
3.2. Viewing Basic Project Information
3.3. Intel® Quartus® Prime Project Contents
3.4. Managing Project Settings
3.5. Managing Logic Design Files
3.6. Managing Timing Constraints
3.7. Integrating Other EDA Tools
3.8. Exporting Compilation Results
3.9. Migrating Projects Across Operating Systems
3.10. Archiving Projects
3.11. Command-Line Interface
3.12. Managing Projects Revision History
3.8.1. Exporting a Version-Compatible Compilation Database
3.8.2. Importing a Version-Compatible Compilation Database
3.8.3. Creating a Design Partition
3.8.4. Exporting a Design Partition
3.8.5. Reusing a Design Partition
3.8.6. Viewing Quartus Database File Information
3.8.7. Clearing Compilation Results
4.1. Design Planning
4.2. Create a Design Specification and Test Plan
4.3. Plan for the Target Device or Board
4.4. Plan for Intellectual Property Cores
4.5. Plan for Standard Interfaces
4.6. Plan for Device Programming
4.7. Plan for Device Power Consumption
4.8. Plan for Interface I/O Pins
4.9. Plan for other EDA Tools
4.10. Plan for On-Chip Debugging Tools
4.11. Plan HDL Coding Styles
4.12. Plan for Hierarchical and Team-Based Designs
4.13. Design Planning Revision History
5.1. IP Catalog and Parameter Editor
5.2. Installing and Licensing Intel® FPGA IP Cores
5.3. IP General Settings
5.4. Adding IP to IP Catalog
5.5. Best Practices for Intel® FPGA IP
5.6. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition)
5.7. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
5.8. Scripting IP Core Generation
5.9. Modifying an IP Variation
5.10. Upgrading IP Cores
5.11. Simulating Intel® FPGA IP Cores
5.12. Generating Simulation Files for Platform Designer Systems and IP Variants
5.13. Synthesizing IP Cores in Other EDA Tools
5.14. Instantiating IP Cores in HDL
5.15. Support for the IEEE 1735 Encryption Standard
5.16. Introduction to Intel FPGA IP Cores Revision History
6.2.1. Modify Entity Name Assignments
6.2.2. Resolve Timing Constraint Entity Names
6.2.3. Verify Generated Node Name Assignments
6.2.4. Replace Logic Lock (Standard) Regions
6.2.5. Modify Signal Tap Logic Analyzer Files
6.2.6. Remove References to .qip Files
6.2.7. Remove Unsupported Feature Assignments
6.4.1. Verify Verilog Compilation Unit
6.4.2. Update Entity Auto-Discovery
6.4.3. Ensure Distinct VHDL Namespace for Each Library
6.4.4. Remove Unsupported Parameter Passing
6.4.5. Remove Unsized Constant from WYSIWYG Instantiation
6.4.6. Remove Non-Standard Pragmas
6.4.7. Declare Objects Before Initial Values
6.4.8. Confine SystemVerilog Features to SystemVerilog Files
6.4.9. Avoid Assignment Mixing in Always Blocks
6.4.10. Avoid Unconnected, Non-Existent Ports
6.4.11. Avoid Illegal Parameter Ranges
6.4.12. Update Verilog HDL and VHDL Type Mapping
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5.5. Best Practices for Intel® FPGA IP
Use the following best practices when working with Intel® FPGA IP:
- Do not manually edit or write your own .qsys, .ip, or .qip file. Use the Intel® Quartus® Prime software tools to create and edit these files.
Note: When generating IP cores, do not generate files into a directory that has a space in the directory name or path. Spaces are not legal characters for IP core paths or names.
- When you generate an IP core using the IP Catalog, the Intel® Quartus® Prime software generates a .qsys (for Platform Designer-generated IP cores) or a .ip file (for Intel® Quartus® Prime Pro Edition) or a .qip file. The Intel® Quartus® Prime Pro Edition software automatically adds the generated .ip to your project. In the Intel® Quartus® Prime Standard Edition software, add the .qip to your project. Do not add the parameter editor generated file (.v or .vhd) to your design without the .qsys or .qip file. Otherwise, you cannot use the IP upgrade or IP parameter editor feature.
- Plan your directory structure ahead of time. Do not change the relative path between a .qsys file and it's generation output directory. If you must move the .qsys file, ensure that the generation output directory remains with the .qsys file.
- Do not add IP core files directly from the /quartus/libraries/megafunctions directory in your project. Otherwise, you must update the files for each subsequent software release. Instead, use the IP Catalog and then add the .qip to your project.
- Do not use IP files that the Intel® Quartus® Prime software generates for RAM or FIFO blocks targeting older device families (even though the Intel® Quartus® Prime software does not issue an error). The RAM blocks that Intel® Quartus® Prime generates for older device families are not optimized for the latest device families.
- When generating a ROM function, save the resulting .mif or .hex file in the same folder as the corresponding IP core's .qsys or .qip file. For example, moving all of your project's .mif or .hex files to the same directory causes relative path problems after archiving the design.
- Always use the Intel® Quartus® Prime ip-setup-simulation and ip-make-simscript utilities to generate simulation scripts for each IP core or Platform Designer system in your design. These utilities produce a single simulation script that does not require manual update for upgrades to Intel® Quartus® Prime software or IP versions, as Simulating Intel FPGA IP Cores describes.