Visible to Intel only — GUID: unr1522372982623
Ixiasoft
Visible to Intel only — GUID: unr1522372982623
Ixiasoft
2. Core Partition Reuse Debug—Developer
Process Description
In this tutorial module, the Developer assigns signals as ports to the partition boundary using the Assignment Editor, and then exports the core partition to a .qdb file. As a result, these user created boundary ports are available for debug as pre-synthesis nodes in the Consumer project, as a part of the reused .qdb file.
Completed Tutorial Files
In the c10_pcie_devkit_design_block_reuse_stp folder, the Core_Partition_Reuse/Completed/Developer/ directory contains the completed files for this tutorial module.
Tutorial Module Steps
This tutorial module includes the following steps:
- Step 1: Creating a Core Partition
- Step 2: Creating Partition Boundary Ports
- Step 3: Compiling and Checking Debug Nodes
- Step 4: Exporting the Core Partition and Creating the Black Box File
- Step 5: Copying Files to Consumer Project
- Step 6: Creating a Signal Tap File (Optional)
- Step 7: Programming the Device and Verifying the Hardware
- Step 8: Verifying Hardware with Signal Tap
- Step 1: Creating a Core Partition
- Step 2: Creating Partition Boundary Ports
- Step 3: Compiling and Checking Debug Nodes
- Step 4: Exporting the Core Partition and Creating the Black Box File
- Step 5: Copying Files to Consumer Project
- Step 6: Creating a Signal Tap File (Optional)
- Step 7: Programming the Device and Verifying the Hardware
- Step 8: Verifying Hardware with Signal Tap