Intel® Advanced Link Analyzer: User Guide

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ID 683448
Date 7/10/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Advanced Link Analyzer Overview 2. Functional Description 3. Tutorial: PCI Express* 8GT 4. Document Revision History for Intel® Advanced Link Analyzer User Guide
1. Intel® Advanced Link Analyzer Overview x
1.1. System Requirements 1.2. Installation 1.3. Program and File Types 1.4. Accessing the User Guide
2. Functional Description x
2.1. Intel® Advanced Link Analyzer Control Module 2.2. Intel® Advanced Link Analyzer Data Viewer Module 2.3. Intel® Advanced Link Analyzer Channel Viewer Module 2.4. Intel® Advanced Link Analyzer Batch Simulation Controller 2.5. Intel® Advanced Link Analyzer Channel Designer
2.1. Intel® Advanced Link Analyzer Control Module x
2.1.1. Constructing Communication Links in the Link Designer Module 2.1.2. Link and Simulation Setting 2.1.3. Transmitter Setting 2.1.4. Receiver Setting 2.1.5. IBIS-AMI Wrapper 2.1.6. Channel Setting 2.1.7. Batch Channel Simulation Configuration 2.1.8. Crosstalk Aggressor Transmitter Setting 2.1.9. Repeater and Retimer Configurations 2.1.10. Noise Source Link Component 2.1.11. System Options 2.1.12. Project Management Functions 2.1.13. Archiving and Unarchiving Projects 2.1.14. Device Model Importer 2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists 2.1.16. COM Analysis
2.1.3. Transmitter Setting x
2.1.3.1. Jitter/Noise Component 2.1.3.2. Transmitter Options 2.1.3.3. Characterization Data Access 2.1.3.4. IBIS-AMI Transmitter Configuration 2.1.3.5. Pulse Fitting Analysis 2.1.3.6. SNDR Analysis 2.1.3.7. Jnu/Jrms/EOJ Analysis 2.1.3.8. Clock Path Custom Transmitter
2.1.4. Receiver Setting x
2.1.4.1. Jitter/Noise Setting 2.1.4.2. Characterization Data Access 2.1.4.3. Receiver Options 2.1.4.4. IBIS-AMI Receiver Configuration 2.1.4.5. Custom Receiver With Input Clock
2.1.9. Repeater and Retimer Configurations x
2.1.9.1. Repeater/Retimer RX Configuration 2.1.9.2. Repeater/Retimer TX Configuration
2.3. Intel® Advanced Link Analyzer Channel Viewer Module x
2.3.1. Channel Plot Panel 2.3.2. Channel List Panel 2.3.3. Plot Option Panel
2.3.3. Plot Option Panel x
2.3.3.1. S-parameter Mode Panel 2.3.3.2. Plot Configuration Panel 2.3.3.3. Options
3. Tutorial: PCI Express* 8GT x
3.1. Methodology 3.2. Setup and Initialization 3.3. Analysis
3.2. Setup and Initialization x
3.2.1. Setting Up the Control Module 3.2.2. Constructing the Channel 3.2.3. Completing the System
1. Intel® Advanced Link Analyzer Overview
2. Functional Description
3. Tutorial: PCI Express* 8GT
4. Document Revision History for Intel® Advanced Link Analyzer User Guide

1. Intel® Advanced Link Analyzer Overview

Updated for:
Intel® Quartus® Prime Design Suite 23.2

Intel® Advanced Link Analyzer is a high-speed transceiver link simulator. When designing high-speed, multi-gigabit transceiver links, you must ensure end-to-end performance from the transmitter (TX) to the receiver (RX) and all interconnects in between.

Intel® Advanced Link Analyzer's graphical user interface (GUI) and link simulator allow you to quickly and easily set up and evaluate high-speed link performance early in your design cycle. Intel® Advanced Link Analyzer also helps you identify possible issues in board-level design. With Intel® Advanced Link Analyzer, you can quickly estimate optimal link equalization and other electrical parameter settings for the transmitter and receiver. You can also use Intel® Advanced Link Analyzer to predict link performance, such as jitter and noise at a small probability level.

Intel® Advanced Link Analyzer can simulate serial links with a clock-forwarding structure, which uses a dedicated clock path to transmit a clock signal that the receiver uses for timing resolution tasks, such as equalization and data determination. To simulate a clock-forwarding serial link, you need a clock signal IBIS-AMI transmitter and an IBIS-AMI receiver model that supports the input clock signal. Currently, Intel® Advanced Link Analyzer supports clock-forwarding IBIS-AMI models as per Buffer Issue Resolution Documents (BIRD) 197, 204, 208, and 209 listed on the IBIS Open Forum.

Note: The clock path simulation support is a beta feature in the Intel® Quartus® Prime software version 23.2.

Section Content
System Requirements
Installation
Program and File Types
Accessing the User Guide

Level Two Title