Intel® Advanced Link Analyzer: User Guide

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ID 683448
Date 7/10/2023
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Document Table of Contents
Document Table of Contents x
1. Intel® Advanced Link Analyzer Overview 2. Functional Description 3. Tutorial: PCI Express* 8GT 4. Document Revision History for Intel® Advanced Link Analyzer User Guide
1. Intel® Advanced Link Analyzer Overview x
1.1. System Requirements 1.2. Installation 1.3. Program and File Types 1.4. Accessing the User Guide
2. Functional Description x
2.1. Intel® Advanced Link Analyzer Control Module 2.2. Intel® Advanced Link Analyzer Data Viewer Module 2.3. Intel® Advanced Link Analyzer Channel Viewer Module 2.4. Intel® Advanced Link Analyzer Batch Simulation Controller 2.5. Intel® Advanced Link Analyzer Channel Designer
2.1. Intel® Advanced Link Analyzer Control Module x
2.1.1. Constructing Communication Links in the Link Designer Module 2.1.2. Link and Simulation Setting 2.1.3. Transmitter Setting 2.1.4. Receiver Setting 2.1.5. IBIS-AMI Wrapper 2.1.6. Channel Setting 2.1.7. Batch Channel Simulation Configuration 2.1.8. Crosstalk Aggressor Transmitter Setting 2.1.9. Repeater and Retimer Configurations 2.1.10. Noise Source Link Component 2.1.11. System Options 2.1.12. Project Management Functions 2.1.13. Archiving and Unarchiving Projects 2.1.14. Device Model Importer 2.1.15. Analysis Functions and Pre-Simulation and Pre-Analysis Checklists 2.1.16. COM Analysis
2.1.3. Transmitter Setting x
2.1.3.1. Jitter/Noise Component 2.1.3.2. Transmitter Options 2.1.3.3. Characterization Data Access 2.1.3.4. IBIS-AMI Transmitter Configuration 2.1.3.5. Pulse Fitting Analysis 2.1.3.6. SNDR Analysis 2.1.3.7. Jnu/Jrms/EOJ Analysis 2.1.3.8. Clock Path Custom Transmitter
2.1.4. Receiver Setting x
2.1.4.1. Jitter/Noise Setting 2.1.4.2. Characterization Data Access 2.1.4.3. Receiver Options 2.1.4.4. IBIS-AMI Receiver Configuration 2.1.4.5. Custom Receiver With Input Clock
2.1.9. Repeater and Retimer Configurations x
2.1.9.1. Repeater/Retimer RX Configuration 2.1.9.2. Repeater/Retimer TX Configuration
2.3. Intel® Advanced Link Analyzer Channel Viewer Module x
2.3.1. Channel Plot Panel 2.3.2. Channel List Panel 2.3.3. Plot Option Panel
2.3.3. Plot Option Panel x
2.3.3.1. S-parameter Mode Panel 2.3.3.2. Plot Configuration Panel 2.3.3.3. Options
3. Tutorial: PCI Express* 8GT x
3.1. Methodology 3.2. Setup and Initialization 3.3. Analysis
3.2. Setup and Initialization x
3.2.1. Setting Up the Control Module 3.2.2. Constructing the Channel 3.2.3. Completing the System
1. Intel® Advanced Link Analyzer Overview
2. Functional Description
3. Tutorial: PCI Express* 8GT
4. Document Revision History for Intel® Advanced Link Analyzer User Guide

2.1.10. Noise Source Link Component

Intel® Advanced Link Analyzer supports noise source generation and simulation in the link level. While most high-speed serial links’ noise are generated by the transmitter and receivers (and their supporting networks and components like power supplies, reference clock, and crosstalk), many industrial standards use external noise sources, which are applied on pre-defined test points within a link, for channel or device compliance tests. Notable industrial standards such as PCISIG and IEEE 802.3 use such external noise injection schemes. With the support of noise source generation and simulation capabilities, we can accurately model such compliance test conditions in Intel® Advanced Link Analyzer.

Figure 90. Noise source GUI entry

Noise source GUI entry shows the GUI entry for noise source generator. Turning Noise Source w/ Channel on makes the Intel® Advanced Link Analyzer Channel Wizard appear (see Noise source channel configuration). By default, an ideal channel (no loss with ideal impedance) is chosen. If there is a channel between the noise generator and the test point, you can click the Change Channel button and select a different channel file. Note that the Signal Source pull-down menu is set to NoiseSouce1 by default. You can also configure or modify the noise source’s relative amplitude, delay, or frequency offset in the same way as setting a crosstalk aggressor. After click OK button, the noise source can be placed in the schematic design space. A typical link topology with a noise source is shown in Typical link topology with a noise source.

Figure 91. Noise source channel configuration
Figure 92. Typical link topology with a noise source
The noise configuration are located in the Aggressor Transmitter tab page (see Noise source configuration). The noise source can be configured with the following parameters:
  • DN: Deterministic noise in mV. DN can be generated using a uniform distribution, dual-Dirac, or truncated Gaussian method. The default DN method is uniform.
  • BUN: Bound uncorrelated noise in mV. The noise characteristics selection is same as DN. The default method is Truncated Gaussian method with a Peak-to-RMS ratio of 14.
  • SN: Sinusoidal noise with peak-peak amplitude in mV with specified frequency in GHz.
  • RN: Random noise in mV-rms. You can further limit the RN bandwidth to the frequency you specify in GHz.
  • Noise PDF: Not supported.
Figure 93. Noise source configuration
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