Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 12/04/2023
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Overview of the Intel® FPGA Power and Thermal Calculator 3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 4. Intel® FPGA Power and Thermal Calculator Graphical User Interface 5. Intel® FPGA Power and Thermal Calculator Pages 6. Factors Affecting the Accuracy of the Intel® FPGA PTC 7. Intel® FPGA Power and Thermal Calculator User Guide Archive 8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
2. Overview of the Intel® FPGA Power and Thermal Calculator x
2.1. Accessing the Intel FPGA Power and Thermal Calculators 2.2. Intel® FPGA PTC Power Model Status 2.3. Definitions of Power Terms Used in this Document
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
3.1. Estimating Power Before Starting the FPGA Design 3.2. Estimating Power While Creating the FPGA Design 3.3. Estimating Power After Completing the FPGA Design 3.4. Estimating Power for Dual-Core Devices
3.2. Estimating Power While Creating the FPGA Design x
3.2.1. Importing a .qptc File Generated in the Intel® Quartus® Prime Power Analyzer
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
4.1. Intel® FPGA PTC Select Family Dialog Box 4.2. Intel® FPGA PTC Primary GUI Components 4.3. Intel® FPGA PTC - IP Wizard 4.4. Intel® FPGA PTC Searchable Drop-Down Lists 4.5. Deleting Rows from Data Entry Pages 4.6. Finding Resources Using the Find Dialog Box
4.2. Intel® FPGA PTC Primary GUI Components x
4.2.1. Intel® FPGA PTC Data Entry Pages 4.2.2. Intel® FPGA PTC Design Hierarchy 4.2.3. Intel® FPGA PTC IP Power Summary 4.2.4. Intel® FPGA PTC Field Types 4.2.5. Intel® FPGA PTC Data Entry Error Messages
4.2.2. Intel® FPGA PTC Design Hierarchy x
4.2.2.1. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 4.2.2.2. Entering Hierarchy Information Into the Intel® FPGA PTC 4.2.2.3. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC 4.2.2.4. Bulk Editing Hierarchies in the Intel FPGA PTC
4.2.4. Intel® FPGA PTC Field Types x
4.2.4.1. Intel® FPGA PTC Input Field Dependencies
5. Intel® FPGA Power and Thermal Calculator Pages x
5.1. Intel® FPGA PTC - Power Summary/Navigation 5.2. Intel® FPGA PTC - Common Page Elements 5.3. Intel® FPGA PTC - Main Page 5.4. Intel® FPGA PTC - Logic Page 5.5. Intel® FPGA PTC - RAM Page 5.6. Intel® FPGA PTC - DSP Page 5.7. Intel® FPGA PTC - Clock Page 5.8. Intel® FPGA PTC - PLL Page 5.9. Intel® FPGA PTC - I/O Page 5.10. Intel® FPGA PTC - Transceiver Page 5.11. Intel® FPGA PTC - HPS Page 5.12. Intel® FPGA PTC - Crypto Page 5.13. Intel FPGA PTC - NOC Page 5.14. Intel® FPGA PTC - HBM Page 5.15. Intel® FPGA PTC - Thermal Page 5.16. Intel® FPGA PTC - Report Page
5.3. Intel® FPGA PTC - Main Page x
5.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
5.10. Intel® FPGA PTC - Transceiver Page x
5.10.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
6. Factors Affecting the Accuracy of the Intel® FPGA PTC x
6.1. Toggle Rate 6.2. I/O Bank Allocation
1. Answers to Top FAQs
2. Overview of the Intel® FPGA Power and Thermal Calculator
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface
5. Intel® FPGA Power and Thermal Calculator Pages
6. Factors Affecting the Accuracy of the Intel® FPGA PTC
7. Intel® FPGA Power and Thermal Calculator User Guide Archive
8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

5.10. Intel® FPGA PTC - Transceiver Page

The Transceiver data entry page of the Intel® FPGA Power and Thermal Calculator (PTC) allows you to enter transceiver resources and their settings for all modules in your design. The power of transceiver I/O pins is included on this page.
Table 20.  General Settings in the Transceiver Page
Input Parameter Description
Total Thermal Power (W) Total power dissipated in all modules on this page (in watts).
Treatment of unused transceivers ( Intel Agilex® Designs Only) For Intel Agilex® designs, specifies how unused transceivers, or used transceivers with unused channels, should be treated. The following options are available:
  • Power Down Unused Transceivers—the power rails of unused transceivers are set to 0V. Not applicable to devices with P-tile and E-tile.
  • Power Up Unused Transceivers—the power rails of unused transceivers are set to a non-zero voltage.
  • Preserve Unused Channels on Used and Unused Transceivers—the power rails of unused transceivers are set to a non-zero voltage and all unused PMA lanes on transceivers are preserved. Selecting Preserve Unused Channels on Used and Unused Transceivers results in the same behavior on the tiles as using the following global .qsf assignment:
    set_global_assignment -name PRESERVE_UNUSED_XCVR_CHANNEL ON
Treatment of Unused HSSI Dies ( Intel® Stratix® 10 Designs Only)

For Intel® Stratix® 10 devices, if you use no transceiver channels or PLLs on an HSSI die, you can power down the die or the die can remain powered. You can select the voltage of unused dies that are powered to minimize static power, or to minimize the number of power supply voltages required.

For example, if active H-tile transceiver channels use VCCR_GXB=1.12V, selecting Minimize Leakage assumes that the unused-but-powered H-tile dies use VCCR_GXB=1.03V, which is the lowest supported voltage, thus minimizing leakage.

Selecting Minimize Number of Supply Voltages assumes that the unused-but-powered banks use VCCR_GXB=1.12V, which is the voltage used by active channels, thus eliminating the need for the 1.03V power supply on VCCR_GXB.

The Intel FPGA PTC uses information in the XCVR Die ID, Starting Channel Location, and # of Channels columns on the XCVR page, along with the # PLL Blocks and XCVR Die ID columns on the PLL page to determine whether dies are actively used. This setting does not apply to E-tile nor P-tile transceivers, because these transceiver dies can never be powered down.

Figure 47. Transceiver Page of the Intel® FPGA PTC (For Intel® Stratix® 10 Designs Only)


Each row in the Transceiver page represents a separate transceiver domain. Enter the following parameters for each transceiver domain:

Table 21.  Transceiver Page Information (For Intel® Stratix® 10 Designs Only)
Column Heading Description
Entity Name Specifies a name for the entity. This is an optional value.
Full Hierarchy Name Specify the hierarchical path relevant to this entry. This is an optional entry. When entering levels of hierarchy, the pipe character (|) denotes a level of hierarchy.
Tile

Specifies the type of transceiver die on which transceiver channels are located. Some devices may include more than one type of transceiver die.

This field changes depending on the device options that you choose on the Main page.

XCVR Die ID Specify the transceiver die on which transceiver channels on this row are located.
Protocol Mode Specifies the mode in which the PCS, HIP, and PCIE blocks operate. This mode depends on the XCVR tile and the communication protocol or standard that the channels on this row implement.
Operation Mode

Specifies whether the hardware is configured in full duplex transceiver mode (receiver and transmitter), Receiver Only mode, or Transmitter Only mode. Allowed values depend on the selected tile and protocol mode.

Modulation Mode Specify the data modulation mode of transceiver channels. This field is applicable only to E-Tile transceivers. When you select High Data Rate PAM4 for this field, 2 physical channels are paired to represent 1 logical channel. When specifying # of Channels, enter the number of physical channels (that is, in multiples of 2).
Starting Channel Location Specify the starting location within the die for the channels specified in this row. For example, if a given row contains 3 channels, and starting location is specified to be 12, channels are assumed to be in locations 12, 13, and 14. Location 0 denotes the bottom-most channel on the transceiver die.
# of PMAs

Specifies the number of physical medium attachments (PMAs) used in this transceiver domain. Each row represents one transceiver domain. These PMAs are grouped together in one transceiver bank, or two or more adjacent transceiver banks and clocked by one or more common transmitter PLLs. For E-tile transceivers, if the selected modulation mode is High Data Rate PAM4, enter 2 physical channels to represent 1 logical channel. (Intel Agilex® 7 devices only.)

For F-tile transceivers:

  • Each PMA with a Digital/Analog Interface Width of less than 40 uses 1 stream.
  • Each PMA with a Digital/Analog Interface Width of 60 uses 2 streams.
  • Each PMA with a Digital/Analog Interface Width of 128 uses 4 streams.

For more information about PMAs and streams, refer to the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.

# of Channels

Specifies the number of channels used in this transceiver domain. Each row represents one transceiver domain. These channels are grouped together in one transceiver bank, or two or more adjacent transceiver banks and clocked by one or more common transmitter PLLs. For E-tile transceivers, if the selected modulation mode is High Data Rate PAM4, enter 2 physical channels to represent 1 logical channel. ( Intel® Stratix® 10 devices only.)

Digital/Analog Interface Width

Specify the width of the parallel data bus between PCS and PMA.

For E-tile PMA Direct, set to PMA parallel data width, even if FPGA FIFO widens the interface. As an example, for 25 Gbps PMA Direct you would typically set this value to 32. When the FEC or EHIP is used, you would set this value to 32 for NRZ mode and 64 for PAM4 mode.

Data Rate (Mbps) Specifies the data rate (in Mbps) for the transceiver. Allowed values depend on the selected protocol mode and selected device.
PLD Clock Frequency (MHz) Specifies the PLD clock frequency. This is applicable only to P-tile transceivers, and when the selected protocol is PCIe gen4.
Power Mode

E-tile transceivers can operate at either Normal Power Mode or Low Power Mode.

For thermal analysis and regulator sizing, you must set the E-tile transceivers in the Normal Power Mode, because your board design must take into consideration the maximum power conditions. Refer to the E-tile Transceiver PHY User Guide for information on how to switch transceivers from Normal Power Mode to Low Power Mode.

FEC Specify the Forward Error Correction setting. This field is applicable only to E-Tile transceivers.
EHIP Specify the Ethernet Hard IP protocol. This field is applicable only to E-Tile and F-Tile transceivers.
Digital Frequency (MHz) Specify the digital frequency at which the digital portion of the transceiver (including FEC and EHIP) operates. This field is applicable only to E-tile transceivers.
# Refclks Specify the number of reference clocks in use. If another interface on this tile is using the same reference clock, and you have already entered this clock in another row, enter 0 in this row to avoid double counting. This field is applicable only to E-Tile transceivers.
Refclk Frequency (MHz) Specify the reference clock frequency. This field is applicable only to E-Tile and F-Tile transceivers.
Application

Specify the application type, which determines values for advanced channel options. Select Custom to enable manual editing of advanced channel options for the current row. This field is applicable only to L-tile and H-tile transceivers.

VCCR_GXB and VCCT_GXB Voltage Specifies the voltage of the VCCR_GXB and VCCT_GXB rails. Allowed values depend on the selected device and selected data rate. This field is applicable only to L-tile and H-tile transceivers.
VOD Setting The output differential voltage (VOD) setting of the transmitter channel PMA. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
VOD Voltage The output differential voltage (VOD) of the transmitter channel PMA (in mV). This voltage depends on the VOD setting and the VCCT_GXB voltage. This field is applicable only to L-tile and H-tile transceivers.
First Pre-Tap Specifies the pre-emphasis setting used by the transmitter channel PMA. Set to Off if the tap value is 0; otherwise, set to On. If pre-emphasis settings are set to On, power consumption does not depend on the magnitude nor the sign (positive or negative) of individual taps. To enable these settings, select Custom in the Application column.
First Post-Tap
DFE Specify mode of the decision feedback equalizer (DFE). Allowed values depend on the selected data rate. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
Adaptation Specify if the adaptation feature is used. This option should be enabled if the channels use either CTLE adaptation or DFE adaptation. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
Transmitter High-Speed Compensation Specifies if the power distribution network (PDN) induced inter-symbol interference (ISI) compensation is enabled in the TX driver. To enable this setting, select Custom in the Application column. This field is applicable only to L-tile and H-tile transceivers.
User Comments Enter any comments. This is an optional entry.
Figure 48. Transceiver Page of the Intel® FPGA PTC (For Intel Agilex® Designs Only)


Each row in the Transceiver page represents a separate transceiver domain. Enter the following parameters for each transceiver domain:

Table 22.  Transceiver Page Information (For Intel Agilex® Designs Only)
Column Heading Description
Entity Name Specifies a name for the entity. This is an optional value.
Full Hierarchy Name Specify the hierarchical path relevant to this entry. This is an optional entry. When entering levels of hierarchy, the pipe character (|) denotes a level of hierarchy.
Transceiver Type

Specifies the type of transceiver on which transceiver channels are located. Some devices may include more than one type of transceiver.

This field changes depending on the device options that you choose on the Main page.

Transceiver ID Specify the transceiver on which transceiver channels on this row are located. The first index indicates bottom (0), middle (1) or top (2), and the second index indicates right (0) or left (1), in package top view with pin A1 at the top-left. For example, HSSI_0_0 is placed at the bottom-right of the package, and HSSI_2_1 is placed at the top-left.
Protocol Mode Specifies the mode in which the PCS, HIP, and UPI blocks operate. This mode depends on the transceiver and the communication protocol or standard that the channels on this row implement.
Operation Mode

Specifies whether the hardware is configured in full duplex transceiver mode (receiver and transmitter), Receiver Only mode, or Transmitter Only mode. Allowed values depend on the selected transceiver type and protocol mode.

Modulation Mode Specify the data modulation mode of transceiver channels.

When you select High Data Rate PAM4 for this field, two physical channels are paired to represent one logical channel. When specifying the number of channels, enter the number of physical channels (that is, in multiples of 2).

This field is applicable only to E-Tile and F-Tile transceivers.

Starting Channel Location Specify the starting location within the transceiver for the channels specified in this row. For example, if a given row contains three channels, and starting location is specified to be 12, channels are assumed to be in locations 12, 13, and 14. Location 0 denotes the bottom-most channel on the transceivers.
# of PMAs

Specifies the number of physical medium attachments (PMAs) used in this transceiver domain. Each row represents one transceiver domain. These PMAs are grouped together in one transceiver bank, or two or more adjacent transceiver banks and clocked by one or more common transmitter PLLs.

For E-tile transceivers, if the selected modulation mode is High Data Rate PAM4, enter two physical channels to represent one logical channel.

For F-tile transceivers:

  • Each PMA with a PCS/PMA Interface width of less than 40 uses one stream.
  • Each PMA with a PCS/PMA Interface width of 64 uses two streams.
  • Each PMA with a PCS/PMA Interface width of 128 uses four streams.

For more information about PMAs and streams, refer to the F-tile Architecture and PMA and FEC Direct PHY IP User Guide.

Digital/Analog Interface Width

Specifies the width of the parallel data bus between PCS and PMA.

For E-tile, F-Tile, and GTS transceiver PMA Direct, set to PMA parallel data width, even if FPGA FIFO widens the interface. As an example, for 25 Gbps PMA Direct, you would typically set this value to 32. When the FEC or EHIP is used, you would set this value to 32 for NRZ mode and 64 for PAM4 mode.

Data Rate (Mbps) Specifies the data rate (in Mbps) for the transceiver. Allowed values depend on the selected protocol mode and selected device.
PLD Clock Frequency (MHz) Specifies the PLD clock frequency. This is applicable only to P-tile transceivers, and when the selected protocol is PCIe gen4.
Power Mode

E-tile transceivers can operate at either Normal Power Mode or Low Power Mode.

For thermal analysis and regulator sizing, you must set the E-tile transceivers in the Normal Power Mode, because your board design must take into consideration the maximum power conditions. Refer to the E-tile Transceiver PHY User Guide for information on how to switch transceivers from Normal Power Mode to Low Power Mode.

FEC Specify the Forward Error Correction setting. This field is applicable only to E-Tile, F-Tile, and GTS transceivers.
EHIP Specify the Ethernet Hard IP protocol. This field is applicable only to E-Tile, F-Tile, and GTS transceivers.
RX Adaptation Specify if RX auto adaptation must be enabled.
Digital Frequency (MHz) Specify the digital frequency that the digital portion of the transceiver (including FEC and EHIP) operates at (in MHz).

Typically, this value is equal to data rate (in Mbps) divided by 64 for E-Tile, or divided by 32 for F-Tile and GTS transceiver. For example, for data rate of 25781.25 Mbps, typical digital frequency is 402.8 MHz (25781.25/64 = 402.8) for E-Tile, or 805.7 MHz (25781.25/32 = 805.7) for F-Tile and GTS transceiver.

This frequency has a minimum requirement of data rate (in Mbps) divided by 2 * PCS/PMA interface width for E-Tile, or divided by PCS/PMA interface width for F-Tile and GTS transceiver. For example, for data rate of 25781.25 Mbps and interface width of 64, the minimum digital frequency is 201.4 MHz (25781.25/(2*64) = 201.4) for E-Tile, or 402.8 MHz (25781.25/64 = 402.8) for F-Tile and GTS transceiver.

# Refclks Specify the number of reference clocks in use. If another interface on this transceiver is using the same reference clock, and you have already entered this clock in another row, enter 0 in this row to avoid double counting.
Refclk Frequency (MHz) Specify the reference clock frequency. This field is applicable only to E-Tile and F-Tile transceivers.
User Comments Enter any comments. This is an optional entry.

For more information about the transceiver architecture of the supported device families, refer to the appropriate Transceiver PHY User Guide for Intel Agilex® devices.


Section Content
Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator

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