Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Overview of the Intel® FPGA Power and Thermal Calculator 3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 4. Intel® FPGA Power and Thermal Calculator Graphical User Interface 5. Intel® FPGA Power and Thermal Calculator Pages 6. Factors Affecting the Accuracy of the Intel® FPGA PTC 7. Intel® FPGA Power and Thermal Calculator User Guide Archive 8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
2. Overview of the Intel® FPGA Power and Thermal Calculator x
2.1. Accessing the Intel FPGA Power and Thermal Calculators 2.2. Intel® FPGA PTC Power Model Status 2.3. Definitions of Power Terms Used in this Document
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
3.1. Estimating Power Before Starting the FPGA Design 3.2. Estimating Power While Creating the FPGA Design 3.3. Estimating Power After Completing the FPGA Design 3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 3.5. Estimating Power for Dual-Core Devices
3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator x
3.4.1. Entering Hierarchy Information Into the Intel® FPGA PTC 3.4.2. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
4.1. Intel® FPGA PTC Select Family Dialog Box 4.2. Intel® FPGA PTC Primary GUI Components 4.3. Deleting Rows from Data Entry Pages
4.2. Intel® FPGA PTC Primary GUI Components x
4.2.1. Intel® FPGA PTC Data Entry Pages 4.2.2. Intel® FPGA PTC Module Manager 4.2.3. Intel® FPGA PTC Field Types 4.2.4. Intel® FPGA PTC Data Entry Error Messages
4.2.3. Intel® FPGA PTC Field Types x
4.2.3.1. Intel® FPGA PTC Input Field Dependencies
5. Intel® FPGA Power and Thermal Calculator Pages x
5.1. Intel® FPGA PTC - Power Summary 5.2. Intel® FPGA PTC - Common Page Elements 5.3. Intel® FPGA PTC - Main Page 5.4. Intel® FPGA PTC - Logic Page 5.5. Intel® FPGA PTC - RAM Page 5.6. Intel® FPGA PTC - DSP Page 5.7. Intel® FPGA PTC - Clock Page 5.8. Intel® FPGA PTC - PLL Page 5.9. Intel® FPGA PTC - I/O Page 5.10. Intel® FPGA PTC - I/O-IP Page 5.11. Intel® FPGA PTC - Transceiver Page 5.12. Intel® FPGA PTC - HPS Page 5.13. Intel® FPGA PTC - Crypto Page 5.14. Intel® FPGA PTC - HBM Page 5.15. Intel® FPGA PTC - Thermal Page 5.16. Intel® FPGA PTC - Report Page
5.3. Intel® FPGA PTC - Main Page x
5.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
5.11. Intel® FPGA PTC - Transceiver Page x
5.11.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
6. Factors Affecting the Accuracy of the Intel® FPGA PTC x
6.1. Toggle Rate 6.2. I/O Bank Allocation
1. Answers to Top FAQs
2. Overview of the Intel® FPGA Power and Thermal Calculator
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface
5. Intel® FPGA Power and Thermal Calculator Pages
6. Factors Affecting the Accuracy of the Intel® FPGA PTC
7. Intel® FPGA Power and Thermal Calculator User Guide Archive
8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

5.1. Intel® FPGA PTC - Power Summary

The Power Summary tile of the Intel® FPGA Power and Thermal Calculator (PTC) displays at all times, and shows the calculated power consumption by resource type.

The values displayed in the Power Summary update in real time as you change parameters on the data entry pages.

In addition to displaying total power consumption, the Power Summary displays power consumption for the resource types listed in the following table.

Table 6.  Resource Types Displayed in the Power Summary
Intel® Agilex™ PTC Power Summary
Resource Type Description
Logic The dynamic power consumed by adaptive logic modules (ALMs), flipflops (FFs) and routing fabric.*
Note: All routing fabric, including from resources other than logic resources is included here.
RAM The dynamic power consumed by specialized blocks optimized for data storage and retrieval.
DSP The dynamic power consumed by specialized blocks optimized for fast math operations.
Clock The dynamic power consumed by clock networks. The clock dynamic power is affected by the selected device.
PLL The dynamic power consumed by phase-locked loops (PLLs).
I/O The dynamic power consumed by I/O pins and I/O subsystems.
Transceiver The dynamic power consumed by transceiver blocks.
HPS The dynamic power consumed by the hard processor system (HPS).
Crypto The dynamic power consumed by the crypto blocks utilized by the design.
HBM The dynamic power consumed by high-bandwidth memory (HBM) and the universal interface bus (UIB) modules.
Static Power The power that the configured device consumes when powered up but with no user clocks operating. The static power (PSTATIC) is the power dissipated on the chip, independent of design activity. PSTATIC includes the static power from all FPGA functional blocks. PSTATIC varies with junction temperature and power characteristics (process). PSTATIC is also the only power component that varies significantly with selected device.
Static Power Savings The package static power savings that occur in standard operation mode. Includes the static power reduction that occurs when not all power rails are at their maximum simultaneously.
SmartVID Power Savings The total power reduction (static and dynamic) resulting from the lower voltage that is made possible by SmartVID. This power reduction is dependent on the user design and device characteristics. The combination of these factors may result in different static and dynamic power savings, so the exact dynamic and static components are not identified separately, and the power reduction reported here is a worst-case result. The reduction reported in this field is already taken into consideration in the Total Power (W) field. The SmartVID Power Savings field applies only to devices that support SmartVID and only when Power Characteristics is set to Maximum.
Total Power The total power dissipated as heat from the FPGA. Does not include power dissipated in off-chip termination resistors. Total power dissipation in the FPGA may differ from the sum of power on all rails due to several factors including, but not limited to, power dissipated in off-chip termination resistors.
Note: For Intel® Agilex™ devices, power reported in a given row of the Power Summary may not always match the total power reported on the corresponding Intel® FPGA PTC data entry page.

Individual Intel® FPGA PTC data entry pages report the total power of resources entered on that page, regardless of the power category to which such power belongs. However, each row of the Power Summary reports power for all pages that contribute power to that category—in addition to any idle power in that category. (Some circuitry on the chip consumes idle power even when the circuitry is unused.)

For example, when implementing an MLAB RAM type on the RAM page, the total power reported on the RAM page includes the power consumed by the memory itself, the power consumed by any additional registers required to implement the memory, as well as any routing power associated with the memory.

On the other hand, the Power Summary reports the following (assuming all other pages are empty):

  • Under the RAM category, power from the RAM page that is due to the memory itself, plus any idle power of all different RAM types in the device.
  • Under the Logic category, power from the RAM page that is due to registers and routing, plus any idle power of all the ALMs, registers and routing in the device.
Intel® Stratix® 10 PTC Power Summary
Resource Type Description
Logic The dynamic power consumed by adaptive logic modules (ALMs), flipflops (FFs) and associated routing.
RAM The dynamic power consumed by RAMs and associated routing.
DSP The dynamic power consumed by digital signal processing (DSP) blocks and associated routing.
Clock The dynamic power consumed by clock networks. The clock dynamic power is affected by the selected device.
PLL The dynamic and standby power consumed by phase-locked loops (PLLs).
I/O The dynamic and standby power consumed by I/O pins and I/O subsystems.
Transceiver The dynamic and standby power consumed by transceiver blocks.
Hard Processor The dynamic and standby power consumed by the hard processor system (HPS).
High-Bandwidth Memory The dynamic power consumed by high-bandwidth memory (HBM) and the universal interface bus (UIB) modules.
Static Power The static power consumed regardless of clock frequency. This includes static power consumed by I/O and transceiver blocks, but does not include standby power.
Total, Before SmartVID Savings The total power consumption before SmartVID power savings. Includes static power (PSTATIC) and power consumed by different blocks as reported above. Does not include power dissipated in off-chip termination resistors.
SmartVID Savings The total power reduction (static and dynamic) resulting from the lower voltage that is made possible by SmartVID. This power reduction is dependent on the user design and device characteristics. The combination of these factors may result in different static and dynamic power savings, so the exact dynamic and static components are not identified separately, and the power reduction reported here is a worst-case result. The reduction reported in this field is already taken into consideration in the Total (W) field. The SmartVID Power Savings field applies only to devices that support SmartVID and only when Power Characteristics is set to Maximum.
Total Power The total power dissipated as heat from the FPGA. Does not include power dissipated in off-chip termination resistors. Total power dissipation in the FPGA may differ from the sum of power on all rails due to several factors including, but not limited to, power dissipated in off-chip termination resistors.
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