Intel® FPGA Power and Thermal Calculator User Guide

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ID 683445
Date 9/26/2022
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Document Table of Contents
Document Table of Contents x
1. Answers to Top FAQs 2. Overview of the Intel® FPGA Power and Thermal Calculator 3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator 4. Intel® FPGA Power and Thermal Calculator Graphical User Interface 5. Intel® FPGA Power and Thermal Calculator Pages 6. Factors Affecting the Accuracy of the Intel® FPGA PTC 7. Intel® FPGA Power and Thermal Calculator User Guide Archive 8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide A. Measuring Static Power
2. Overview of the Intel® FPGA Power and Thermal Calculator x
2.1. Accessing the Intel FPGA Power and Thermal Calculators 2.2. Intel® FPGA PTC Power Model Status 2.3. Definitions of Power Terms Used in this Document
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator x
3.1. Estimating Power Before Starting the FPGA Design 3.2. Estimating Power While Creating the FPGA Design 3.3. Estimating Power After Completing the FPGA Design 3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator 3.5. Estimating Power for Dual-Core Devices
3.4. Using Design Hierarchies in the Intel® FPGA Power and Thermal Calculator x
3.4.1. Entering Hierarchy Information Into the Intel® FPGA PTC 3.4.2. Exporting, Importing, Duplicating, Renaming, and Deleting Hierarchies in the Intel® FPGA PTC
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface x
4.1. Intel® FPGA PTC Select Family Dialog Box 4.2. Intel® FPGA PTC Primary GUI Components 4.3. Deleting Rows from Data Entry Pages
4.2. Intel® FPGA PTC Primary GUI Components x
4.2.1. Intel® FPGA PTC Data Entry Pages 4.2.2. Intel® FPGA PTC Module Manager 4.2.3. Intel® FPGA PTC Field Types 4.2.4. Intel® FPGA PTC Data Entry Error Messages
4.2.3. Intel® FPGA PTC Field Types x
4.2.3.1. Intel® FPGA PTC Input Field Dependencies
5. Intel® FPGA Power and Thermal Calculator Pages x
5.1. Intel® FPGA PTC - Power Summary 5.2. Intel® FPGA PTC - Common Page Elements 5.3. Intel® FPGA PTC - Main Page 5.4. Intel® FPGA PTC - Logic Page 5.5. Intel® FPGA PTC - RAM Page 5.6. Intel® FPGA PTC - DSP Page 5.7. Intel® FPGA PTC - Clock Page 5.8. Intel® FPGA PTC - PLL Page 5.9. Intel® FPGA PTC - I/O Page 5.10. Intel® FPGA PTC - I/O-IP Page 5.11. Intel® FPGA PTC - Transceiver Page 5.12. Intel® FPGA PTC - HPS Page 5.13. Intel® FPGA PTC - Crypto Page 5.14. Intel® FPGA PTC - HBM Page 5.15. Intel® FPGA PTC - Thermal Page 5.16. Intel® FPGA PTC - Report Page
5.3. Intel® FPGA PTC - Main Page x
5.3.1. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
5.11. Intel® FPGA PTC - Transceiver Page x
5.11.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
6. Factors Affecting the Accuracy of the Intel® FPGA PTC x
6.1. Toggle Rate 6.2. I/O Bank Allocation
1. Answers to Top FAQs
2. Overview of the Intel® FPGA Power and Thermal Calculator
3. Estimating Power Consumption with the Intel® FPGA Power and Thermal Calculator
4. Intel® FPGA Power and Thermal Calculator Graphical User Interface
5. Intel® FPGA Power and Thermal Calculator Pages
6. Factors Affecting the Accuracy of the Intel® FPGA PTC
7. Intel® FPGA Power and Thermal Calculator User Guide Archive
8. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power

5.11.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator

You can estimate E-tile channel PLL power for Intel® Stratix® 10 devices, by adding a Transmitter-only row to the Transceiver page of the Intel® FPGA Power and Thermal Calculator (PTC).

The following three examples illustrate the Intel® FPGA PTC configuration for various E-tile channel PLL requirements.

Table 18.  E-Tile Channel PLL configured for: Reference clock = 200MHz, pll_clkout1 = 800MHz, pll_clkout2 = 400MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 12800 16 Normal Power Bypass Bypass NRZ 0 1 200 0
Table 19.  E-Tile Channel PLL configured for: Reference clock = 125MHz, pll_clkout1 = 500MHz, pll_clkout2 = 250MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 8000 16 Normal Power Bypass Bypass NRZ 0 1 125 0
Table 20.  E-Tile Channel PLL configured for: Reference clock = 307MHz, pll_clkout1 = 491MHz, pll_clkout2 = 245MHz
Operation Mode Data Rate Digital/Analog Width Power Mode FEC EHIP Modulation Digital Freq # Refclks Refclk Freq VOD
Transmitter Only 19660.8 40 Normal Power Bypass Bypass NRZ 0 1 307 0

Alternatively, you can instantiate an E-Tile Transceiver-native PHY IP in PLL mode in your Intel® Quartus® Prime project, compile the project, and view the configuration in the Intel® FPGA PTC.

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