Visible to Intel only — GUID: sky1607105720155
Ixiasoft
1. Overview of the Intel® FPGA Power and Thermal Calculator
2. Setting Up the Intel® FPGA Power and Thermal Calculator
3. Intel® FPGA Power and Thermal Calculator Graphical User Interface
4. Intel® FPGA Power and Thermal Calculator Pages
5. Factors Affecting the Accuracy of the Intel® FPGA Power and Thermal Calculator
6. Intel® FPGA Power and Thermal Calculator User Guide Archive
7. Document Revision History for the Intel® FPGA Power and Thermal Calculator User Guide
A. Measuring Static Power
4.1. Intel® FPGA PTC - Power Summary
4.2. Intel® FPGA PTC - Common Page Elements
4.3. Intel® FPGA PTC - Device Selection and Thermal Analysis Windows
4.4. Intel® FPGA PTC - Main Page
4.5. Intel® FPGA PTC - Logic Page
4.6. Intel® FPGA PTC - RAM Page
4.7. Intel® FPGA PTC - DSP Page
4.8. Intel® FPGA PTC - Clock Page
4.9. Intel® FPGA PTC - PLL Page
4.10. Intel® FPGA PTC - I/O Page
4.11. Intel® FPGA PTC - I/O-IP Page
4.12. Intel® FPGA PTC - Transceiver Page
4.13. Intel® FPGA PTC - HPS Page
4.14. Intel® FPGA PTC - Crypto Page ( Intel® Agilex™ Devices with Crypto Blocks Only)
4.15. Intel® FPGA PTC - HBM Page ( Intel® Stratix® 10 Devices Only)
4.16. Intel® FPGA PTC - Thermal Page
4.17. Intel® FPGA PTC - Report Page
Visible to Intel only — GUID: sky1607105720155
Ixiasoft
4.12.1. Estimating E-Tile Channel PLL Power with the Intel Power and Thermal Calculator
You can estimate E-tile channel PLL power for Intel® Stratix® 10 devices, by adding a Transmitter-only row to the Transceiver page of the Intel® FPGA Power and Thermal Calculator (PTC).
The following three examples illustrate the PTC configuration for various E-tile channel PLL requirements.
Operation Mode | Data Rate | Digital/Analog Width | Power Mode | FEC | EHIP | Modulation | Digital Freq | # Refclks | Refclk Freq | VOD |
---|---|---|---|---|---|---|---|---|---|---|
Transmitter Only | 12800 | 16 | Normal Power | Bypass | Bypass | NRZ | 0 | 1 | 200 | 0 |
Operation Mode | Data Rate | Digital/Analog Width | Power Mode | FEC | EHIP | Modulation | Digital Freq | # Refclks | Refclk Freq | VOD |
---|---|---|---|---|---|---|---|---|---|---|
Transmitter Only | 8000 | 16 | Normal Power | Bypass | Bypass | NRZ | 0 | 1 | 125 | 0 |
Operation Mode | Data Rate | Digital/Analog Width | Power Mode | FEC | EHIP | Modulation | Digital Freq | # Refclks | Refclk Freq | VOD |
---|---|---|---|---|---|---|---|---|---|---|
Transmitter Only | 19660.8 | 40 | Normal Power | Bypass | Bypass | NRZ | 0 | 1 | 307 | 0 |
Alternatively, you can instantiate an E-Tile Transceiver-native PHY IP in PLL mode in your Intel® Quartus® Prime project, compile the project, and view the configuration in the PTC.