Intel® FPGA SDK for OpenCL™: Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

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ID 683435
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide x
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform 1.2. Porting the Reference Platform to Your SoC FPGA Board 1.3. Software Support for Shared Memory 1.4. FPGA Reconfiguration 1.5. Building an SD Flash Card Image 1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA 1.7. Known Issues 1.8. Document Revision History
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform x
1.1.1. Cyclone V SoC Development Kit Reference Platform Board Variants 1.1.2. Content of the Cyclone V SoC Development Kit Reference Platform 1.1.3. Relevant Features of the Cyclone V SoC Development Kit
1.1.3. Relevant Features of the Cyclone V SoC Development Kit x
1.1.3.1. Cyclone V SoC Development Kit Reference Platform Design Goals and Decisions
1.2. Porting the Reference Platform to Your SoC FPGA Board x
1.2.1. Updating a Ported Reference Platform
1.4. FPGA Reconfiguration x
1.4.1. FPGA System Architecture Details
1.5. Building an SD Flash Card Image x
1.5.1. Modifying an Existing SD Flash Card Image 1.5.2. Creating an SD Flash Card Image
1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA x
1.6.1. Recompiling the Linux Kernel 1.6.2. Compiling and Installing the OpenCL Linux Kernel Driver
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

1.2.1. Updating a Ported Reference Platform

In the current version of the Cyclone® V SoC Development Kit Reference Platform, the HPS block is inside the partition that defines all nonkernel logic. However, you cannot export the HPS as part of the .qxp file. To update an existing Custom Platform that you modified from a previous version of c5soc, implement the QXP preservation flow, update the SD flash card image to obtain the latest runtime environment, and update the board_spec.xml file to enable automigration.
The Altera® SDK for OpenCL™ version 14.1 and beyond probes the board_spec.xml file for board information, and implements automatic updates. Because you modify the design by implementing the QXP preservation flow, you must update the board_spec.xml file to its format in the current version. Updating the file allows the SDK to distinguish between unpreserved Custom Platforms and the current QXP-based Custom Platforms. Refer to Custom Platform Automigration for Forward Compatibility in the Intel® FPGA SDK for OpenCL™ Custom Platform Toolkit User Guide for more information.
  1. To implement the QXP preservation flow in a Cyclone V SoC FPGA hardware design that is ported from a previous version of c5soc, perform the following steps to create a subpartition to exclude the HPS from the .qxp file:
    1. Before creating a partition around the nonkernel logic, create a partition around the HPS in the .qsf Intel® Quartus® Prime Settings File.
      For example: 
        # Manually partition the instance that models the HPS-dedicated I/O
set_instance_assignment -name PARTITION_HIERARCHY borde_18261 -to
"system:the_system|system_acl_iface:acl_iface|system_acl_iface_hps_0:hps_0|system_acl_iface_hps_0_hps_io:hps_io|system_acl_iface_hps_0_hps_io_border:border" -section_id "system_acl_iface_hps_0_hps_io_border:border"

  # Set partition to be an HPS_PARTITION type to be processed correctly by the rest of Quartus
  set_global_assignment -name PARTITION_TYPE HPS_PARTITION -section_id "system_acl_iface_hps_0_hps_io_border:border"
      Modify the setting accordingly because your design hierarchy might be different from the example.
    2. When exporting the partition for acl_iface_partition, include the --incremental_compilation_export_flatten=off option to leave the HPS partition as a blackbox. 
      quartus_cdb top -c top 
--incremental_compilation_export=acl_iface_partition.qxp 
--incremental_compilation_export_partition_name=acl_iface_partition 
--incremental_compilation_export_post_synth=on 
--incremental_compilation_export_post_fit=on 
--incremental_compilation_export_routing=on 
--incremental_compilation_export_flatten=off
      After you exclude the HPS from the partition, you may import the .qxp file and compile your design.
  2. Update the SD flash card image with the current version of the Intel® FPGA RTE for OpenCL by performing the following tasks:
    1. Mount the file allocation table (fat32) and extended file system (ext3) partitions in the existing image as loop-back devices. For detailed instructions, refer to Step 2 in Building an SD Flash Card Image.
    2. In the /home/root/opencl_arm32_rte directory, remove the files from the previous version of the RTE.
    3. Download and unpack the current verison of the RTE into the /home/root/opencl_arm32_rte directory.
    4. In the <path_Custom_Platform>/driver/version.h file of your Custom Platform, update the ACL_DRIVER_VERSION assignment to <SDK_version>.<driver_version> (for example, 16.1.x, where 16.1 is the SDK verison, and x is the driver version that you set).
    5. Rebuild the driver.
    6. Delete the hardware folder(s) of your Custom Platform. Copy the Custom Platform, along with the updated driver, to the /home/root/opencl_arm_rte/board directory.
    7. Copy the Altera.icd file from the /home/root/opencl_arm32_rte directory and add it to the /etc/OpenCL/vendors directory.
    8. Unmount and test the new image. For detailed instructions, refer to Steps 8 to 11 in Building an SD Flash Card Image.
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