Intel® FPGA SDK for OpenCL™: Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

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ID 683435
Date 11/06/2017
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Document Table of Contents
Document Table of Contents x
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide x
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform 1.2. Porting the Reference Platform to Your SoC FPGA Board 1.3. Software Support for Shared Memory 1.4. FPGA Reconfiguration 1.5. Building an SD Flash Card Image 1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA 1.7. Known Issues 1.8. Document Revision History
1.1. Overview of the Cyclone V SoC Development Kit Reference Platform x
1.1.1. Cyclone V SoC Development Kit Reference Platform Board Variants 1.1.2. Content of the Cyclone V SoC Development Kit Reference Platform 1.1.3. Relevant Features of the Cyclone V SoC Development Kit
1.1.3. Relevant Features of the Cyclone V SoC Development Kit x
1.1.3.1. Cyclone V SoC Development Kit Reference Platform Design Goals and Decisions
1.2. Porting the Reference Platform to Your SoC FPGA Board x
1.2.1. Updating a Ported Reference Platform
1.4. FPGA Reconfiguration x
1.4.1. FPGA System Architecture Details
1.5. Building an SD Flash Card Image x
1.5.1. Modifying an Existing SD Flash Card Image 1.5.2. Creating an SD Flash Card Image
1.6. Compiling the Linux Kernel for Cyclone V SoC FPGA x
1.6.1. Recompiling the Linux Kernel 1.6.2. Compiling and Installing the OpenCL Linux Kernel Driver
1. Intel® FPGA SDK for OpenCL™ Intel® Cyclone® V SoC Development Kit Reference Platform Porting Guide

1.7. Known Issues

Currently, there are certain limitations on the usage of the Intel® FPGA SDK for OpenCL™ with the Cyclone® V SoC Development Kit Reference Platform.
  1. You cannot override the vendor and board names reported by the CL_DEVICE_VENDOR and CL_DEVICE_NAME strings of the clGetDeviceInfo() call.
  2. If the host allocates constant memory in shared DDR system (that is, HPS DDR) and it modifies the constant memory after kernel execution, the data in memory might become outdated. This issue arises because the FPGA core cannot snoop on CPU-to-HPS DDR transactions.

    To prevent subsequent kernel executions from accessing outdated data, implement one of the following workarounds:

    • Do not modify constant memory after its initialization.
    • If you require multiple __constant data sets, create multiple constant memory buffers.
    • If available, allocate constant memory in the FPGA DDR on your accelerator board.
  3. The SDK utility on ARM® only supports the program and diagnose utility commands.

    The flash, install and uninstall utility commands are not applicable to the Cyclone V SoC Development Kit for the following reasons:

    1. The install utility has to compile the aclsoc_drv Linux kernel driver and enable it on the SoC FPGA. The development machine has to perform the compilation; however, it already contains Linux kernel sources for the SoC FPGA. The Linux kernel sources for the development machine are different from those for the SoC FPGA. The location of the Linux kernel sources for the SoC FPGA is likely unknown to the SDK user. Similarly, the uninstall utility is also unavailable to the Cyclone V SoC Development Kit.

      Also, delivering aclsoc_drv to the SoC board is challenging because the default distribution of the Cyclone V SoC Development Kit does not contain Linux kernel include files or the GNU Compiler Collection (GCC) compiler.

    2. The flash utility requires placing a .rbf file of an OpenCL design onto the FAT32 partition of the micro SD flash card. Currently, this partition is not mounted when the SDK user powers up the board. Therefore, the best way to update the partition is to use a flash card reader and the development machine.
  4. When switching between the Intel® FPGA SDK for OpenCL™ Offline Compiler executable files (.aocx) that correspond to different board variants (that is, c5soc and c5soc_sharedonly), you must use the SDK's program utility to load the .aocx file for the new board variant for the first time. If you simply run the host application using a new board variant but the FPGA contains the image from another board variant, a fatal error might occur.
  5. The .qxp file does not include the interface partition assignments because the Intel® Quartus® Prime software consistently meets timing requirements of this partition.
  6. When you power up the board, its media access control (MAC) address is set to a random number. If your LAN policy does not allow this behavior, set the MAC address by performing the following tasks:
    1. During U-Boot power-up, press any key to enter the U-Boot command prompt.
    2. Type setenv ethaddr 00:07:ed:00:00:03 at the command prompt.

      You may choose any MAC address.

    3. Type the saveenv command.
    4. Reboot the board.
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